Logic Systems and Processors

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Code Completion Credits Range Language
BE5B35LSP Z,ZK 6 3P+2L English
It is not possible to register for the course BE5B35LSP if the student is concurrently registered for or has already completed the course B0B35LSP (mutually exclusive courses).
During a review of study plans, the course B0B35LSP can be substituted for the course BE5B35LSP.
It is not possible to register for the course BE5B35LSP if the student is concurrently registered for or has previously completed the course B0B35LSP (mutually exclusive courses).
Garant předmětu:
Richard Šusta
Martin Hlinovský, Richard Šusta
Martin Hlinovský, Richard Šusta
Department of Control Engineering

The course introduces the basic hardware structures of computing resources, their design, and architecture. It provides an overview of the possibilities of performing data operations at the hardware level and the design of embedded processor systems with peripherals on modern FPGA programmable logic circuits, which are increasingly widely used today. Students will learn their description in VHDL, from logic to more complex sequential circuits to practical finite state machine (FSM) designs. They will also master the correct design procedure using circuit simulation. Practical problems are solved using development boards used at hundreds of leading universities around the world. The course ends with RISC-V processor structure, cache, and pipeline processing.


Basic knowledge of Boolean algebra and logic circuits.

Syllabus of lectures:

1. The structure of computer systems. Logical expressions versus logic gates. Logical cube and build logic functions of Karnaugh maps. Group minimization. Boolean algebra. De Morgan theorem. SAT problem and Shannon expansion. Binary Decision Diagrams.

2. VHDL language to describe circuits, basic design. Descriptions of basic combinational circuits in the schemes and VHDL.

3. Implementation of basic combinational logic circuits for computers and their descriptions in the schemes and VHDL. Sequential circuits.

4. Sequential circuits and their basic types. Latch-type flip-flops and Master-Slave.

5. Describe in VHDL Behavioral style, registers, and counters.

6. Basic sequential circuits computers. Memory and their structure in VHDL.

7. Implementation of circuits within the FPGA. Problems with the concurrence of parallel operations in logic circuits. Metastability circuit. Elements used in 3rd and 4th project.

8. professional manner for testing and simulation of VHDL programs, ie. Creating Testbench. Using ModelSim simulation breakpoints and stepping in VHDL programs.

9. FSM (Finite State Machine) - genesis, Mealy and Moore automata. Solving machines in VHDL. Tasks leading to FSMs, design and testing machines.

10. From a controller to the processor. Data path. Activity Example 1bitového CPU processor and its testing.

11. The structure of soft-core processor on the chip, its usage and modifications.

12. Processor peripherals and connectivities, internal bus circuits.

13. Advanced CPU and features to build custom embedded systems processor.

14.-Basics interfacing with, or difficulties connecting circuits. Protections of inputs and outputs, problems with the wires, buses and various types of loads. Power Solution and countries. Galvanic isolation.

Syllabus of tutorials:

Students receive credits in practical exercises by solving individual projects on FPGA development boards Altera DE2; which are utilized by dozens of the world's leading universities. License terms for programming the Altera Quartus II environment and allow its installation on the home computer students.

Study Objective:

Introduction to the structure of computer technology and the basics of simple design of computer peripherals.

Study materials:

1. Volnei A. Pedroni: Digital Electronics and Design with VHDL, MORGAN KAUFMANN 2008, ISBN: 0123742706

2. Enoch O. Hwang: Digital Logic and Microprocessor Design with VHDL, Thomson 2006, ISBN: 0-534-46593-5

3. Šusta R.: APOLOS - prerequisite, ČVUT-FEL 2013

Further information:
Time-table for winter semester 2023/2024:
Šusta R.
Hlinovský M.

(lecture parallel1)
Karlovo nám.
Laboratoř TŘ2
Šusta R.
Hlinovský M.

(lecture parallel1
parallel nr.101)

Karlovo nám.
Laboratoř AB
Time-table for summer semester 2023/2024:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2024-07-23
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