Logo ČVUT
CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2023/2024
UPOZORNĚNÍ: Jsou dostupné studijní plány pro následující akademický rok.

Logic systems and processors

Login to KOS for course enrollment Display time-table
Code Completion Credits Range Language
B0B35LSP Z,ZK 6 2P+2L Czech

It is not possible to register for the course B0B35LSP if the student is concurrently registered for or has already completed the course BE5B35LSP (mutually exclusive courses).

It is not possible to register for the course B0B35LSP if the student is concurrently registered for or has previously completed the course BE5B35LSP (mutually exclusive courses).

The requirement for course B0B35LSP can be fulfilled by substitution with the course BE5B35LSP.

Garant předmětu:
Zdeněk Hurák
Lecturer:
Martin Hlinovský, Richard Šusta
Tutor:
Martin Hlinovský, Richard Šusta
Supervisor:
Department of Control Engineering
Synopsis:

The course introduces computing resources' basic hardware structures, design, and architecture. It provides an overview of the possibilities of performing data operations at the hardware level and designing embedded processor systems with peripherals on modern FPGA programmable logic circuits, which are increasingly widely used today.

Students will learn their description in VHDL, from logic to more complex sequential circuits to practical finite state machine (FSM) designs. They will also master the correct design procedure using circuit simulation. Practical problems are solved using development boards that hundreds of leading universities worldwide also use.

The course ends with RISC-V processor structure, cache, and pipeline processing.

[last updated January 2024]

Requirements:

Boolean algebra, logic circuits

Syllabus of lectures:

1. Introduction. The logical cube and equations of logical functions from the Karnaugh maps.

2. De Morgan's theorem and its application. Shannon's expansion. Basic building blocks and structure of FPGA circuits.

3. From C to VHDL: basic notation, number conversion, and multiplexer usage.

4. Examples of the use of concurrent statements. Introduction to the 2nd practice problem.

5. Sequential domain of VHDL.

6. Gate delays. Gambling in combinational circuits and the need to eliminate them with synchronous circuits. Latches and synchronous per rising edge. Their usage in VHDL.

7. Basic synchronous circuits with DFF, feelings.

8. Shift registers and examples of their use.

9. From counters up down through controllers to general Finite State Machine (FSM) of Moore type.

10. Communication between FSMs, from FSM to processor controllers.

11. The structure of the RISC V processor, its basic 32I version, and the instruction flow.

12. The processor memory system: the cache.

13. Memory paging. Instruction pipelining, data hazards, and branch predictors.

14. Advanced FPGA design topics - soft-core processors.

[last updated January 2024]

Syllabus of tutorials:
Study Objective:

Introduction into computers systems and basic constructions of computers peripherials.

Study materials:
Note:
Further information:
https://dcenet.fel.cvut.cz/edu/fpga/
Time-table for winter semester 2023/2024:
Time-table is not available yet
Time-table for summer semester 2023/2024:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomKN:E-23
Hlinovský M.
Šusta R.

09:15–10:45
(lecture parallel1
parallel nr.107)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Hlinovský M.
Šusta R.

11:00–12:30
(lecture parallel1
parallel nr.108)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
Hlinovský M.

14:30–16:00
(lecture parallel1
parallel nr.101)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
Hlinovský M.

16:15–17:45
(lecture parallel1
parallel nr.102)

Karlovo nám.
Laboratoř AB
Tue
Wed
roomKN:E-23
Hlinovský M.
Šusta R.

11:00–12:30
(lecture parallel1
parallel nr.103)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Hlinovský M.
Šusta R.

12:45–14:15
(lecture parallel1
parallel nr.104)

Karlovo nám.
Laboratoř AB
Thu
roomKN:E-107
Šusta R.
Hlinovský M.

11:00–12:30
(lecture parallel1)
Karlovo nám.
Zengerova posluchárna K1
roomKN:E-23
Hlinovský M.
Šusta R.

12:45–14:15
(lecture parallel1
parallel nr.105)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
Hlinovský M.

14:30–16:00
(lecture parallel1
parallel nr.106)

Karlovo nám.
Laboratoř AB
roomT2:C3-135
Šusta R.
Hlinovský M.

11:00–12:30
(lecture parallel1)
Dejvice
T2:C3-135
Fri
The course is a part of the following study plans:
Data valid to 2024-05-18
Aktualizace výše uvedených informací naleznete na adrese https://bilakniha.cvut.cz/en/predmet4666506.html