Systems on Chip
- The course cannot be taken simultaneously with:
- Embedded Software (NI-ESW)
- Garant předmětu:
- Department of Digital Design
Students gain key knowledge and skills in the design of large-scale digital systems. They will be familiar with architectures of such systems and communication among their parts. They will use an appropriate workflow to design these architectures, their hardware and software. They will also have knowledge of contemporary methods of large systems verification and fault-tolerant systems design.
Design and test of combinational and synchronous sequential digital circuits and corresponding workflows. System modeling and modeling languages. Basic overview of verification methods.
- Syllabus of lectures:
1. A taxonomy and characteristics of systems on a chip (SoC). Common requirements to SoC. Implementation platforms, granularity.
2. On the chip communications, quantitative approach.
3. Hardware-software decomposition, design space exploration.
4. Harware-software codesign methods and metrics.
5. Real-time systems, architectures, properties.
6. Real-time operation systems (RTOS), fault-tolerant software.
7. Fault-tolerant systems, Dependability models and method of dependability characteristics´ computations.
8. System-level timing and synchronization.
9. Networks on chip (NoC), routing protocols and their implementation.
10. Low-power design.
11. SoC modeling and verification methods. Software-hardware co-verification.
12. Verification by simulation, simulation cover monitoring and control, stimuli generation methods.
13. Practical applications.
- Syllabus of tutorials:
1. Team construction and project topic selection close to SoC.
2. Practical HW/SW Co-Design (Xilinx Zynq)
3. Processor design in CODASIP
5. Consultations of partial results
6. Semestral team project prezentation
7. Project review and discussion
- Study Objective:
Modern highly integrated digital systems are designed to achieve high performance, small dimensions, and low energy consumption. The module brings knowledge required to design both the software and the hardware of such systems, because both areas are tightly coupled. Nevertheless, design is only a small part of the game. „We will die of verification“ was heard at conferences as early as in 2000, in reference to difficult verification of system correctness. Therefore, we present the contemporary state-of-the-art in this area, as it is necessary for verification engineers. The last part of the course is dedicated to the construction of dependable systems for critical applications.
- Study materials:
1. Pasricha, S., Dutt, N. ''On-Chip Communication Architectures: System on Chip Interconnect''. Morgan Kaufmann, 2008. ISBN 012373892X.
2. Erbas, G. ''System-Level Modeling and Design Space Exploration for Multiprocessor Embedded System-on-Chip Architectures''. Amsterdam University Press, 2006. ISBN 9056294555.
- Further information:
- No time-table has been prepared for this course
- The course is a part of the following study plans:
- Master branch Knowledge Engineering, in Czech, 2016-2017 (elective course)
- Master branch Computer Security, in Czech, 2016-2019 (elective course)
- Master branch Computer Systems and Networks, in Czech, 2016-2019 (elective course)
- Master branch Design and Programming of Embedded Systems, in Czech, 2016-2019 (compulsory course of the specialization)
- Master branch Web and Software Engineering, spec. Info. Systems and Management, in Czech, 2016-2019 (elective course)
- Master branch Web and Software Engineering, spec. Software Engineering, in Czech, 2016-2019 (elective course)
- Master branch Web and Software Engineering, spec. Web Engineering, in Czech, 2016-2019 (elective course)
- Master program Informatics, unspecified branch, in Czech, version 2016-2019 (VO)
- Master branch System Programming, spec. System Programming, in Czech, 2016-2019 (elective course)
- Master branch System Programming, spec. Computer Science, in Czech, 2016-2017 (elective course)
- Master specialization Computer Science, in Czech, 2018-2019 (elective course)
- Master branch Knowledge Engineering, in Czech, 2018-2019 (elective course)