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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2024/2025
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Welcome page > Faculty of Information Technology > Department of Digital Design > Practical Digital Design

Practical Digital Design

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Code Completion Credits Range Language
BI-PNO.21 KZ 5 2P+2C Czech
Garant předmětu:
Martin Novotný
Lecturer:
Martin Novotný
Tutor:
Stanislav Jeřábek, Martin Novotný
Supervisor:
Department of Digital Design
Synopsis:

Students get an overview of the contemporary digital design flow and learn practical skills to use synchronous design techniques. They understand the basics of the VHDL language and implementation technologies FPGA and ASIC. Students demonstrate practical use of the design techniques in the course project using modern industry-standard CAD design tools.

Requirements:

Basic knowledge of architectures of computers and their units and of digital system design techniques.

Syllabus of lectures:

1. Contemporary digital design flow.

2. Project management, metrics, and estimates.

3. Fundamentals of synchronous design.

4. Digital circuit implementation technologies - ASICs, FPGAs.

5. Design at the algorithm level, decomposition to blocks.

6. The VHDL language for description of digital circuits.

7. Circuit description on the RT level - registers, counters, multiplexers.

8. Circuit description on the RT level - arithmetics.

9. Circuit description on the RT level - on-chip memories.

10. Synthesis from the RT level - the use of constraints.

11. Verification plan, models of verification.

12. Implementation of a testbench.

13. Design for testability.

Syllabus of tutorials:

1. Students will get practical experience in the design of digital circuits using EDA tools for FPGAs. Students will work out a semestral project and accomplish a short visit in a professional design center.

2. Introduction to the subject.

3. [3] Introduction and exercises with FPGA EDA tool.

4. [3] Design and verification of a simple synchronous circuit.

5. [5] Individual work on the semestral project.

6. Visit to a professional digital design center.

7. Presentation of the results.

8. Evaluation.

Study Objective:

The main aim is to obtain practical skills in using modern, industry-standard CAD design tools, that is, to produce synthesizable design in VHDL and implement it in a FPGA.

Study materials:

1. Ashenden P. J. : The designer's guide to VHDL (3rd Edition). Morgan Kaufmann, 2008. ISBN 978-01208878591.

2. Jasinski R. : Eective coding with VHDL: principles and best practice. MIT Press, 2016. ISBN 978-0262034227.

3. Readler B. C. : VHDL by Example: A Concise Introduction for FPGA Design. Full Arc Press, 2014. ISBN978-0983497356.

Note:
Further information:
https://courses.fit.cvut.cz/BI-PNO/
Time-table for winter semester 2024/2025:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Wed
roomTH:A-1042
Novotný M.
12:45–14:15
(lecture parallel1)
Thákurova 7 (budova FSv)
Hlavickova laborkaroomTH:A-1042
Novotný M.
Jeřábek S.
14:30–16:00
(lecture parallel1
parallel nr.101)
Thákurova 7 (budova FSv)
Hlavickova laborka
Thu
Fri
Time-table for summer semester 2024/2025:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2024-10-06
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