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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2024/2025
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Welcome page > Faculty of Information Technology > Department of Computer Systems > Architectures of Computer Systems

Architectures of Computer Systems

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Code Completion Credits Range Language
BI-APS.21 Z,ZK 5 2P+2C Czech
Course guarantor:
Pavel Tvrdík
Lecturer:
Michal Štepanovský, Pavel Tvrdík
Tutor:
Michal Štepanovský, Pavel Tvrdík
Supervisor:
Department of Computer Systems
Synopsis:

Students will learn the construction principles of internal architecture of computers with universal processors at the level of machine instructions. Special emphasis is given on the pipelined instruction processing and on the memory hierarchy. Students will understand the basic concepts of RISC and CISC architectures and the principles of instruction processing not only in scalar processors, but also in superscalar processors that can execute multiple instructions in one cycle, while ensuring the correctness of the sequential model of the program. The course further elaborates the principles and architectures of shared memory multiprocessor and multicore systems and the memory coherence and consistency in such systems.

Requirements:

Basic knowledge of combinational and sequential logical circuits. Knowledge of basic instruction cycle and assembly labguage programming. Programing in C, the role of a compiler for a higher level PL.

Syllabus of lectures:

1. Quantitative principles of computer design, Amdahl’s law, computer performance evaluation, benchmarks.

2. Instruction set architectures: taxonomy RISC processors vs. CISC processors, assembly language.

3. Verilog as a hardware description language: syntax and semantics.

4. Incremental design of a single-cycle RISC processor, principles and basic implementations of CPU control units.

5. Design of a simple pipelined RISC processor, hazards in the pipeline and their elimination.

6. Memory hierarchy: Cache memory principle, various implementations (direct-mapped, fully associative, N-way set-associative).

7. Memory hierarchy: Virtual memory (paging) and its HW support in memory management units of conventional CPUs.

8. Multicore CPUs and multiprocessor systems. Cache memory coherence, the MESI protocol, directory-based coherence.

10. Memory consistency and the sequential consistency model. Synchronization instructions for accessing shared memory.

11. Superscalar CPUs I: Introduction to instruction-level parallelism. Static (in-order) and dynamic (out-of-order) instruction execution, register renaming (Tomasulo's algorithm).

12. Superscalar CPUs II: Memory-referencing instructions, load bypassing and load forwarding, speculative loads from memory. Memory consistency for multi-core CPUs.

13. Superscalar CPUs III: Branch prediction, speculative instruction prefetching and execution.

Syllabus of tutorials:

1. Evaluation of computer performance

2. ISA and the MIPS assembly language

3. Programming in assembly language for MIPS

4. Hardware description language (Verilog)

5. Basic components of simple RISC processors

6. Pipelined processor

7. Cache memory viewed by CPU/assembler

8. Cache memory viewed by a C/C++ programmer

9. MESI coherence protocol

10. Memory consistency and synchronization primitives

11. Memory consistency viewed by a C/C++ programmer

12. Superscalar processors

13. Semestral projects check, assessment

Study Objective:
Study materials:

1. Patterson D. A., Hennessy J. L. : Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2014. ISBN 978-0128012857.

2. Hennessy J.L., Patterson D.A. : Computer Architecture: A Quantitative Approach (6th Edition). Morgan Kaufmann, 2017. ISBN 978-0128119051.

3. Shen J. P., Lipasti M. H. : Modern Processor Design. Fundamentals of Superscalar Processors. Waveland Press, 2013. ISBN 978-1478607830.

I

Note:
Further information:
https://courses.fit.cvut.cz/BI-APS
Time-table for winter semester 2024/2025:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomTH:A-1042
Štepanovský M.
11:00–12:30
(lecture parallel1
parallel nr.101)
Thákurova 7 (budova FSv)
Hlavickova laborkaroomTH:A-1042
Štepanovský M.
12:45–14:15
(lecture parallel1
parallel nr.102)
Thákurova 7 (budova FSv)
Hlavickova laborkaroomTH:A-1042
Štepanovský M.
16:15–17:45
(lecture parallel1
parallel nr.103)
Thákurova 7 (budova FSv)
Hlavickova laborkaroomTH:A-1042
Štepanovský M.
18:00–19:30
(lecture parallel1
parallel nr.104)
Thákurova 7 (budova FSv)
Hlavickova laborka
Tue
roomTH:A-1042
Štepanovský M.
11:00–12:30
(lecture parallel1
parallel nr.105)
Thákurova 7 (budova FSv)
Hlavickova laborkaroomT9:155
Štepanovský M.
16:15–17:45
(lecture parallel1)
Dejvice
Posluchárna
roomTH:A-1042
Štepanovský M.
12:45–14:15
(lecture parallel1
parallel nr.106)
Thákurova 7 (budova FSv)
Hlavickova laborka
Wed
Thu
Fri
Time-table for summer semester 2024/2025:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2024-10-12
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