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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2024/2025
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Welcome page > Faculty of Information Technology > Department of Digital Design > Testing and Reliability

Testing and Reliability

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Code Completion Credits Range Language
NI-TSP Z,ZK 5 2P+2C Czech
Course guarantor:
Petr Fišer
Lecturer:
Petr Fišer
Tutor:
Martin Daňhel, Petr Fišer
Supervisor:
Department of Digital Design
Synopsis:

Students will gain knowledge about circuit testing and about methods for increasing reliability and security. They will get practical skills to be able to prepare a test set with the help of the intuitive path sensitization and to use an ATPG for automatic test generation. They will be able to design easily testable circuits and systems with built-in-self-test equipment. They will be able to compute, analyze, and control the reliability and availability of the designed circuits.

Requirements:

Digital IC design (BIE-SAP).

Syllabus of lectures:

1. Introduction, terminology, defects, faults

2. Test generation for combinational circuits

3. Automatic Test Patterns Generation algorithms (ATPG)

4. Sequential circuits testing, fault simulation

5. Dependability, increasing dependability

6. Dependability models, dependability computation

7. Design for testability

8. Sequential circuit testing - scan design

9. Interconnect testing, SoC and NoC testing

10. Built-in self-test (BIST)

11. Test compression

12. Memory and FPGA testing

Syllabus of tutorials:

1. Introduction to the course

2. Faults in digital circuits

3. Tests generation for combinational circuits, D-Algorithm

4. ATPG Atalanta, Boolean Differential calculus

5. SAT-based ATPG

6. Testing of sequential circuits

7. Reliability Block Diagrams

8. Markov reliability models

9. Fault Tree Analysis and other reliability models

10. Reliability standards

11. Assessment test, BIST design

12. Assessment

Study Objective:

Students will gain an overview of circuit testing and methods for increasing reliability and dependability. Students will understand the complexity of fault detection, fault localization, reliability evaluation, and enhancement by solving practical examples and projects. They will be able to optimize the trade-off between introduced redundancy and the measure of testability and dependability of the proposed system. Students will obtain a competence for getting a position of testing engineer in the teams working on complex digital designs.

Study materials:

O. Novák, E. Gramatová, and R. Ubar, „Handbook of testing electronic systems“. Praha: Publishing House of CTU, 2005. ISBN 80-01-03318-X.

R. Velazco, D. McMorrow, J. Estela, „Radiation Effects on Integrated Circuits and Systems for Space Applications“, Springer, 2019, ISBN: 978-3-030-04660-6, 401 p.

Z. Navabi, „Digital System Test and Testable Design“, Springer, 2011, ISBN 978-1-4419-7547-8, p. 435

L. D., Protheroe D., „Digital circuit testing and design for testability“, in Design of Logic Systems, Springer, Boston, MA, ISBN: 978-0-412-42890-6, 1992

F. C. Wang, „Digital Circuit Testing: A Guide to DFT and Other Techniques“, Elsevier, ISBN 978-0-12-734580-2, 1991, 228 p.

F. da Silva, T. McLaurin, and T Waayers, „The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500“, Frontiers in Electronic Testing, 2006-th Edition, Springer, ISBN 978-0387307510, 2006, 276 p.

Note:
Further information:
https://courses.fit.cvut.cz/NI-TSP/
Time-table for winter semester 2024/2025:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomTH:A-942
Fišer P.
12:45–14:15
(lecture parallel1)
Thákurova 7 (budova FSv)
Tue
Wed
Thu
roomTH:A-1048
Daňhel M.
18:00–19:30
(lecture parallel1
parallel nr.102)
Thákurova 7 (budova FSv)
HW lab mag.
Fri
Time-table for summer semester 2024/2025:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2024-12-17
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