Seminars on Architectures of Parallel Computers

The course is not on the list Without time-table

Code	Completion	Credits	Range
XP36SEP	ZK	4	2P

Course guarantor:

Lecturer:

Tutor:

Supervisor:

Department of Computer Science

Synopsis:

Overview of architectures of high-performance computers and trends in

technologies. Memory coherence and sequential consistency models.

Shared-memory architectures: buses and switches, bus-based cache coherence

protocols and synchronization mechanisms. Virtual shared memory

architectures: distributed cache-coherence protocols. Synchronization

mechanisms - barriers. Clusters: fast communication networks and protocols.

Requirements:

Syllabus of lectures:

1. Memory coherence and consistency models.

2. Shared memory architectures: fast busses and switches.

3. Shared memory architectures: coherence snooping algorithms.

4. Shared memory architectures: synchronization mechanisms.

6.-8. Virtual Shared memory architectures: cache coherence protocols.

9.-11. Distributed memory architectures: synchronization mechanisms and algorithms.

12.-14. Workstation clusters: fast interconnects and network protocols.

Syllabus of tutorials:

Study Objective:

Study materials:

D.E.Culler, et al. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publ., 1999, ISBN 1-55860-343-3.

Note:

Further information:

No time-table has been prepared for this course

The course is a part of the following study plans: