Digital Circuit Simulation and Verification

Garant předmětu:

Martin Kohlík

Přednášející:

Martin Kohlík

Cvičící:

Martin Kohlík

Předmět zajišťuje:

katedra číslicového návrhu

Anotace:

Aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers today recent verification methods, too.

Požadavky:

Design methods for combinational and sequential logic circuits, knowledge of number representations, and knowledge of the circuit implementations of basic arithmetic operations.

Osnova přednášek:

1. Fundamental simulation and verification principles.

2. Simulation languages VHDL and Verilog.

3. Sequential and paralel simulation environment.

4. Hierarchical structure specification, parametrization.

5. Functions, procedures, and events in simulation models.

6. Design checking, using of assertions.

7. Verilog/SystemVerilog: introduction, data types, comparisons.

8. Communication between modules, transactions.

9. Simulation management, random and delimited stimulus generation, coverage control.

10. Advanced design control in simulation, assertion in SystemVerilog.

11. Universal Verification Methodology (UVM).

12. Advanced constructions, register model.

Osnova cvičení:

1. Introduction, VHDL/Verilog project - Assignment.

2. VHDL/Verilog project - Consultation.

3. VHDL/Verilog project - Evaluation.

4. Test 1 - VHDL/Verilog, Verilog/SystemVerilog project - Assignment.

5. Verilog/SystemVerilog project - Consultation.

6. Test 2 - Verilog/SystemVerilog, Verilog/SystemVerilog project - Evaluation.

Cíle studia:

The goal of the course is to acquaint students with the properties of the above-mentioned languages and their use for verification (simulation).

Studijní materiály:

1. Mehta, A. B.: SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications. Springer, 2016. ISBN 9783319305394.

2. Mehta, A. B.: ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. Springer, 2018. ISBN 9783319594187.

3. Mehler, R.: Digital Integrated Circuit Design Using Verilog and Systemverilog (1st Edition). Elsevier, 2014. ISBN 9780124095298.

4. Cohen, B. - Kumari, S. V. A. - Piper, L.: SystemVerilog Assertions Handbook (3rd Edition). VhdlCohen Publishing, 2013. ISBN 978-0-9705394-3-6.

Poznámka:

Course information and teaching materials can be found at https://courses.fit.cvut.cz/MI-SIM/

Další informace:

https://courses.fit.cvut.cz

Rozvrh na zimní semestr 2024/2025:

Rozvrh není připraven

Rozvrh na letní semestr 2024/2025:

Rozvrh není připraven

Předmět je součástí následujících studijních plánů:

• Master specialization Software Engineering, in English, 2021 (volitelný předmět)
• Master specialization Computer Security, in English, 2021 (volitelný předmět)
• Master specialization Computer Systems and Networks, in English, 2021 (volitelný předmět)
• Master specialization Design and Programming of Embedded Systems, in English, 2021 (PS)
• Master specialization Computer Science, in English, 2021 (VO)
• Master specialization Computer Science, in English, 2024 (VO)