Design for the FPGA and ASIC Technology
- Garant předmětu:
- Department of Digital Design
Students gain the basic knowledge needed to start a career in a design house. They will understand the FPGA and ASIC implementation technologies and the limitations that the technologies impose on the design. They are able to perform and to manage typical workflows, their analytic and synthetic steps, with an emphasis on basic verification. They know the structure and demands of software tools, as well as what to expect from them.
Gates and registers, basic CMOS circuits, simple gate-level design, finite state machine and its synchronous implementation.
- Syllabus of lectures:
1. The gist of hardware design. The role and types of decomposition. Synthetic and analytic steps. Basic economy of product design and manufacturing.
2. CMOS circuits, dynamic behavior, power consumption. Technology characterization. Implementation of programmable combinational function and programmable interconnect.
3. Synchronous digital design, timing, models. Clock domains, signal transfer across clock domain boundary. Metastablility.
4. Top-down and bottom-up design process, its steps and iteration loops. Hardware project management, metrics. Intellectual property cores. Reuse methodology.
5. Programmable devices: overview, usage, programming methods. SPLD and CPLD devices.
6. FPGA devices: architecture, logical blocks, interconnect, blocks performing computation and communication, memory blocks. Dynamic behavior.
7. Design styles for ASICs. The impact of deep submicron technologies. ASIC design tools.
8. ASIC and FPGA workflow comparison, key differences.
9. Verification techniques: formal techniques (model checking, equivalence checking), advanced simulation, assertions, hybrid assertion-based techniques.
10. Physical design: routing, placement, technology mapping.
11. Logic synthesis, basic phases, used formalisms. Timing-driven and power-driven synthesis.
12. Behavioral synthesis, areas of use.
13. System-level design, hardware-software decomposition and codesign, design by model refinement.
- Syllabus of tutorials:
1. Lab: getting started with equipment, software and kits
2. Lab: synchronous FPGA design
3. Lab: synchronous FPGA design
4. Lab: FPGA design with multiple clock domains
5. Lab: FPGA design with multiple clock domains
6. Lab: FPGA design with multiple clock domains
7. Lab: FPGA design with given speed and external timing
8. Lab: FPGA design with given speed and external timing
9. Lab: FPGA design with given speed and external timing
10. Lab: verification
11. Lab: verification
12. Lab: verification
13. Lab: verification
14. Presentation of results, evaluation
- Study Objective:
The module builds a bridge from the basic digital design, which students have learned earlier, to the level where the students will understand professional designers. They will gain insight into the interplay between technology, software tools, workflow, and the quality of the result.
- Study materials:
1. Wilson, P. ''Design Recipes for FPGAs''. Newnes, 2007. ISBN 0750668458.
- Further information:
- No time-table has been prepared for this course
- The course is a part of the following study plans:
- Master branch Knowledge Engineering, in Czech, 2016-2017 (elective course)
- Master branch Computer Security, in Czech, 2016-2019 (elective course)
- Master branch Computer Systems and Networks, in Czech, 2016-2019 (elective course)
- Master branch Design and Programming of Embedded Systems, in Czech, 2016-2019 (compulsory course of the specialization)
- Master branch Web and Software Engineering, spec. Info. Systems and Management, in Czech, 2016-2019 (elective course)
- Master branch Web and Software Engineering, spec. Software Engineering, in Czech, 2016-2019 (elective course)
- Master branch Web and Software Engineering, spec. Web Engineering, in Czech, 2016-2019 (elective course)
- Master program Informatics, unspecified branch, in Czech, version 2016-2019 (VO)
- Master branch System Programming, spec. System Programming, in Czech, 2016-2019 (elective course)
- Master branch System Programming, spec. Computer Science, in Czech, 2016-2017 (elective course)
- Master specialization Computer Science, in Czech, 2018-2019 (elective course)
- Master branch Knowledge Engineering, in Czech, 2018-2019 (elective course)