Logical Simulation
The course is not on the list Without time-table
| Code | Completion | Credits | Range |
|---|---|---|---|
| XP36LSM | ZK | 4 | 2P+2S |
- Garant předmětu:
- Lecturer:
- Tutor:
- Supervisor:
- Department of Computer Science
- Synopsis:
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General introduction to simulation: fundamental ideas and principles of simulation systems, synchronous and asynchronous simulation. Simulation system VHDL and its use for simulation of digital circuits: data types, entities, architectures, sequential environment (processes, functions, procedures), signals and their attributes, resolution function, parallel environment (data-flow description, blocks, structural description), configuration of structural models.
Students who completed course 36SIM cannot enroll.
- Requirements:
- Syllabus of lectures:
- Syllabus of tutorials:
- Study Objective:
- Study materials:
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1. Cohen Ben: VHDL Coding Styles and Methodologies, Springer 1999
2. Zwolinski Mark: Digital System Design with VHDL, Prentice Hall 2003
- Note:
- Further information:
- No time-table has been prepared for this course
- The course is a part of the following study plans:
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- Doctoral studies, daily studies (compulsory elective course)
- Doctoral studies, combined studies (compulsory elective course)
- Doctoral studies, structured daily studies (compulsory elective course)
- Doctoral studies, structured combined studies (compulsory elective course)