ACDRC FrontEnd Workshop

Course guarantor:

Jiří Jakovenko

Lecturer:

Jiří Jakovenko

Tutor:

Vladimír Janíček

Supervisor:

Department of Microelectronics

Synopsis:

This hands-on workshop delves into the world of Electronic Design Automation (EDA) and Analog Circuit Design, equipping participants with essential techniques to optimize circuit performance. Explore key concepts such as design optimization, PPAR & variation, and backend EDA workflows, alongside powerful algorithms for floorplanning, partitioning, placement, and routing. Gain practical insights into layout automation and circuit design strategies to streamline your development process. Whether you're a beginner or looking to refine your expertise, this workshop will help you design smarter, faster, and more efficiently in todays competitive electronics industry!

Requirements:

Syllabus of lectures:

Day 1:

Introduction to IC Design Flow and Challenges in Digital Logic Optimization

Boolean Representation: ROBDD and ITE operator

Syllabus of tutorials:

Day 2:

Two-level Optimization: Quine McCluskey and Petricks Method

Lab1: Implementation and Practice on Quine McCluskey Algorithm

Day 3:

Multi-level Optimization: Kernels, Co-kernels, and Boolean Division

Lab2: Opensource Logic Optimization Tool - ABC

Study Objective:

Study materials:

Note:

Further information:

No time-table has been prepared for this course

The course is a part of the following study plans: