ACDRC Smart EDA & Analog Circuit Design Workshop: From Fundamentals to Optimization
The course is not on the list Without time-table
| Code | Completion | Credits | Range | Language |
|---|---|---|---|---|
| JASSSEAC | Z | 1 | 12P+12C | English |
- Course guarantor:
- Jiří Jakovenko
- Lecturer:
- Jiří Jakovenko
- Tutor:
- Vladimír Janíček
- Supervisor:
- Department of Microelectronics
- Synopsis:
- Requirements:
- Syllabus of lectures:
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Day 1: Foundations of EDA & Analog Chip Design
09:00 12:00 What is EDA? A quick glance
13:00 16:00 Introduction to Analog Chip Design and Its Challenges
Day 2: Circuit Partitioning and Floorplanning
09:00 12:00 Partitioning and Floorplanning: a tree-based approach
13:00 16:00 Hand-on practice: Slicing-tree based circuit floorplan
Day 3
09:00 12:00 Placement and Routing: SA-based approach
13:00 16:00 Hand-on practice: Current source array placement
- Syllabus of tutorials:
- Study Objective:
- Study materials:
- Note:
- Further information:
- No time-table has been prepared for this course
- The course is a part of the following study plans: