Advanced Integrated System Design

Course guarantor:

Jiří Jakovenko

Lecturer:

Dalibor Barri, Jiří Jakovenko

Tutor:

Dalibor Barri

Supervisor:

Department of Microelectronics

Synopsis:

The course focuses on the complex process of integrated circuit design from theoretical foundations to practical physical implementations (layouts). The lectures gradually discuss the principles of chip design, the differences between discrete and integrated technologies, CMOS and BCD technologies, the methodology for the correct design of transistors and circuit structures, advanced approaches to power MOS transistors and building blocks (reference circuits, dividers, mixed-signal elements, stability).

Other parts are devoted to the design of linear voltage regulators (LDO), protections (OCP, eFuse, ESD), issues of parasitic phenomena, chip topologies and physical design methods including automation and programming in Python. The course also covers issues of testing, error diagnostics and economic aspects of chip production.

Exercises provide practical experience with the Cadence Virtuoso design environment and the SKILL language. The course covers the complete design of an integrated LDO regulator with current protection, including a detailed design of a power transistor and a feedback resistor divider. They also focus on advanced current mirrors, circuit stability solutions and the gradual addition of protection mechanisms. Within the framework of physical design, the creation of power structures of MOSFETs, paired elements and programmable resistor dividers is practiced, followed by verification (DRC, LVS). The course is concluded with practical exercises focused on the automation of analog design of integrated circuits.

Requirements:

Syllabus of lectures:

1. The birth of a new chip; hierarchy design, the difference between discrete and integrated technology, description of BCD and CMOS technologies, advanced view of the basic building blocks of integrated circuit design.

2. Proper design practices mirroring, cascoding, transistor dimensions, pair structures, current carrying capacity, Rdson, Common Mode+CASC, dimension scaling for digital and analog circuits, accuracy.

3. Advanced design of power integrated MOS transistors in analog circuits, types of power MOS transistors, voltage class of power transistors, description of copy MOS transistors.

4. Advanced design of building blocks part I Starter circuit, accurate voltage and current reference, advanced configurability.

5. Advanced design of building blocks part II Advanced configurability, dividers, circuits in Mix mode (ADC, DAC, etc.).

6. Advanced Design of Building Blocks Part III Description of Methods to Ensure Circuit Stability

7. Advanced Design of IP Block I - Linear Voltage Regulator (LDO), Electronic Fuses (eFuse), Over Current Protection (OCP)

8. Chip as a Minefield: ESD Protection, Latch-Up Resistance, Trimming, Testability; Parasitic Structures, Contribution Layout Simulation.

9. Advanced Chip Topology Design - Analog TOP, Digital TOP; Layout-Dependent Effects (WPE, STI, wSTI, Ant. Diode, PID, Metallization); floor plan (methodology, input output blocks, pad placement)

10. Methods for automating the layout of the physical design of integrated circuits

11. Methods for automating the layout of the physical design of integrated circuits in the Python programming language

12. Basic „golden“ rules for the physical design of integrated circuits

13. Methods for analyzing errors in IC design: Electrical diagnostic methods, reproduction, Optical, electron microscopy, SAW, X-ray, IR, Obirch, LASER cutting, FIB cutting + deposition, metal fix.

14. Possibilities of chip implementation, necessary inputs, economic side.

Syllabus of tutorials:

1. Introduction to the SKILL programming language in the Virtuoso Cadence development environment

2. Description of the proposed chip (LDO with OCP), precise design of a feedback configurable resistor divider

3. Precise design of a power transistor respecting the conditions for a given LDO structure and with requirements for RDS_ON

4. Advanced design of an LDO with a simple current mirror

5. Advanced design of an LDO with a cascode current mirror

6. Circuit stability solution - part I

7. Circuit stability solution - part II

8. Supplementing the advanced design of an LDO with a cascode current mirror with current protection (OCP)

9. Physical design of a power MOSFET transistor including conductive layers (metal layers)

10. Physical design of a resistor divider used in an LDO (programmable resistor divider)

11. Physical design of paired structures in an LDO topology (differential stage, current mirror with cascode)

12. Physical Design Verification, DRC, LVS

13. Automated Layout of Analog Integrated Circuit Design - Part I

14. Automated Layout of Analog Integrated Circuit Design - Part II

Study Objective:

Study materials:

Recommended references:

Analog design:

1) Razavi: Design of Analog CMOS Integrated Circuits, McGRAW-Hill,

2) Murari, F. Bertotti, G.A.Vignola: Smart Power ICs, Springer,

3) Gray, P Hurst, s. Lewis, R. Mayer: Analysis and Design of Analog Integrated Circuits, John Wiley and Sons.

Analog design:

1) Analysis and Design of Analog Integrated Circuits, 5th Edition, by J. Paul R. Gray, Paul J. Hurst, Stephen H.

Lewis, Robert G. Meyer

2) Analog Integrated Circuit Design, by Tony Chan Carusone, David Johns, Kenneth Martin

Analog layout:

1) The Art of Analog Layout, by Alan Hastings

2) Fundamentals of Power Semiconductor Devices, by BJ Baliga

3) Analog-to-Digital Conversion, by Marcel J.M. Pelgrom

Digital design:

1) P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008

Note:

Time-table for winter semester 2025/2026:

	06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Wed	roomT2:B2-s141k Jakovenko J. Barri D. 09:15–10:45 (lecture parallel1) Dejvice roomT2:C3-s143 Barri D. 11:00–12:30 (lecture parallel1 parallel nr.101) Dejvice roomT2:C3-s143 Barri D. 12:45–14:15 (lecture parallel1 parallel nr.102) Dejvice roomT2:B2-s141k Jakovenko J. Barri D. 09:15–10:45 (lecture parallel1) Dejvice
Thu
Fri

Time-table for summer semester 2025/2026:

Time-table is not available yet

The course is a part of the following study plans:

• Electronics and Communications - Electronics (compulsory elective course)
• Electronics and Integrated Systems (compulsory elective course)