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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2023/2024

Computer Structures and Architectures

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Code Completion Credits Range Language
BIE-SAP.21 Z,ZK 5 2P+1R+2C English
Garant předmětu:
Petr Fišer
Lecturer:
Petr Fišer
Tutor:
Elizaveta Denisova, Petr Fišer, Peter Guľa, Olha Harielina, Martin Kohlík, Tomáš Přeučil
Supervisor:
Department of Digital Design
Synopsis:

Students understand basic digital computer units and their structures, functions, and hardware implementation: ALU, control unit, memory system, inputs, outputs, data storage and transfer. In the labs, students gain practical experience with the design and implementation of the logic of a simple processor using modern digital design tools.

Requirements:

Input knowledge: Basic knowledge of physical principles of digital circuits (transistors as switches, implementation of registers, data storage principles) and fundamentals of discrete mathematics (number representation systems, Boolean algebra).

Syllabus of lectures:

1. Introduction, basic architecture of a computer, data representation.

2. Logic functions and their descriptions, combinatorial circuits, implementation using gates.

3. Sequential circuits. Synchronous design, implementation using gates and flip-flops. Mealy and Moore automata.

4. Typical combinatorial and sequential components of a computer, their implementations (encoder, adder, counter, register).

5. Data, its representation and processing.

6. Arithmetic operations with signed numbers. Fix-point and floating point numbers.

7. Implementation of arithmetic operations.

8. Memories - memory cell structure, static and dynamic memories.

9. Cache memories, virtual memory system.

10. Instructions and machine code.

11. Instruction set architecture, addressing modes.

12. Interrupts, buses.

13. Control units, basic types of processors.

Syllabus of tutorials:

1. Adders, gates, practical implementation.

2. Boolean algebra, minimization, gates.

3. Combinatorial circuits, converters.

4. Minimization, gate-level design, logic functions.

5. Sequential circuits, counter, sequence matching.

6. Sequential design, graph of transitions, table, implementation using D-type flip-flops and gates.

7. Architecture of the AVR processor, sample program.

8. Arithmetics, addition, negative numbers, overflow, complement code.

9. Program - shifts, ASCII.

10. Test, project assignment. Assembler.

11. Project work - display.

12. Arithmetic programs, shifts, control of peripherals.

13. Project result presentations.

Study Objective:

The module teaches basic knowledge of digital computer construction principles, how a computer performs its operations, what the machine code is and how it is related to higher programming languages.

Study materials:

1. Patterson D. A., Hennessy J. L. : Computer Organization and Design: The Hardware/Software Interface (5th Edition). Morgan Kaufmann, 2014. ISBN 978-0128012857.

2. Wakerly J. F. : Digital Design: Principles and Practices (5th Edition). Pearson, 2018. ISBN 978-0134460093.

3. Mano M.M., Ciletti M.D. : Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog (6th Edition). Pearson, 2017. ISBN 978-0134549897.

Note:
Time-table for winter semester 2023/2024:
Time-table is not available yet
Time-table for summer semester 2023/2024:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomT9:155
Fišer P.
12:45–14:15
ODD WEEK

(lecture parallel1
parallel nr.101)

Dejvice
Posluchárna
roomT9:111
Fišer P.
18:00–19:30
(lecture parallel1)
Dejvice
Posluchárna
Tue
roomTH:A-1042
Guľa P.
Denisova E.

09:15–10:45
(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Hlavickova laborka
roomTH:A-1042
Guľa P.
Harielina O.

12:45–14:15
(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Hlavickova laborka
roomTH:A-1048
Přeučil T.
09:15–10:45
(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Servitova laborka
Wed
roomTH:A-1042
Guľa P.
Harielina O.

09:15–10:45
(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Hlavickova laborka
roomTH:A-1048
Guľa P.
14:30–16:00
(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Servitova laborka
Thu
Fri
The course is a part of the following study plans:
Data valid to 2024-05-25
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