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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2023/2024
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Digital Circuit Simulation and Verification

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Code Completion Credits Range Language
NI-SIM Z,ZK 5 2P+1C Czech
Garant předmětu:
Martin Kohlík
Lecturer:
Martin Kohlík
Tutor:
Martin Kohlík
Supervisor:
Department of Digital Design
Synopsis:

The aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers recent verification methods, too.

Requirements:

Design methods for combinational and sequential logic circuits, knowledge of number representations, and knowledge of the circuit implementations of basic arithmetic operations.

Syllabus of lectures:

1. Fundamental simulation and verification principles.

2. Simulation languages VHDL and Verilog.

3. Sequential and paralel simulation environment.

4. Hierarchical structure specification, parametrization.

5. Functions, procedures, and events in simulation models.

6. Design checking, using of assertions.

7. Verilog/SystemVerilog: introduction, data types, comparisons.

8. Communication between modules, transactions.

9. Simulation management, random and delimited stimulus generation, coverage control.

10. Advanced design control in simulation, assertion in SystemVerilog.

11. Universal Verification Methodology (UVM).

12. Advanced constructions, register model.

Syllabus of tutorials:

1. Introduction, VHDL/Verilog project - Assignment.

2. VHDL/Verilog project - Consultation.

3. VHDL/Verilog project - Evaluation.

4. Test 1 - VHDL/Verilog, Verilog/SystemVerilog project - Assignment.

5. Verilog/SystemVerilog project - Consultation.

6. Test 2 - Verilog/SystemVerilog, Verilog/SystemVerilog project - Evaluation.

Study Objective:

The goal of the course is to acquaint students with the properties of the above-mentioned languages and their use for verification (simulation).

Study materials:

Mehta, A. B. : SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications. Springer, 2016. ISBN 9783319305394.

Mehta, A. B. : ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. Springer, 2018. ISBN 9783319594187.

Mehler, R. : Digital Integrated Circuit Design Using Verilog and Systemverilog (1st Edition). Elsevier, 2014. ISBN 9780124095298.

Cohen, B. - Kumari, S. V. A. - Piper, L. : SystemVerilog Assertions Handbook (3rd Edition). VhdlCohen Publishing, 2013. ISBN 978-0-9705394-3-6.

Note:
Further information:
https://courses.fit.cvut.cz/MI-SIM/
Time-table for winter semester 2023/2024:
Time-table is not available yet
Time-table for summer semester 2023/2024:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomTH:A-1442
Kohlík M.
11:00–12:30
(lecture parallel1)
Thákurova 7 (budova FSv)
roomTH:A-1048
Kohlík M.
18:00–19:30
EVEN WEEK

(lecture parallel1
parallel nr.101)

Thákurova 7 (budova FSv)
Servitova laborka
roomTH:A-1048
Kohlík M.
18:00–19:30
ODD WEEK

(lecture parallel1
parallel nr.102)

Thákurova 7 (budova FSv)
Servitova laborka
Tue
Wed
Thu
Fri
The course is a part of the following study plans:
Data valid to 2024-03-27
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