Digital Circuit Simulation and Verification

Garant předmětu:

Lecturer:

Tutor:

Supervisor:

Department of Digital Design

Synopsis:

The aim of the course is to acquaint the students with principles of digital circuit simulation at RTL (Register Transfer Level) and TLM (Transaction Level Modeling) levels and with the properties of proper tools. The course covers recent verification methods, too.

Requirements:

Design methods for combinational and sequential logic circuits, knowledge of number representations, and knowledge of the circuit implementations of basic arithmetic operations.

Syllabus of lectures:

1. Fundamental simulation and verification principles.

2. Simulation languages VHDL and Verilog.

3. Sequential and paralel simulation environment.

4. Hierarchical structure specification, parametrization.

5. Functions, procedures, and events in simulation models.

6. Design checking, using of assertions.

7. Verilog/SystemVerilog: introduction, data types, comparisons.

8. Communication between modules, transactions.

9. Simulation management, random and delimited stimulus generation, coverage control.

10. Advanced design control in simulation, assertion in SystemVerilog.

11. Universal Verification Methodology (UVM).

12. Advanced constructions, register model.

Syllabus of tutorials:

1. Introduction, VHDL/Verilog project - Assignment.

2. VHDL/Verilog project - Consultation.

3. VHDL/Verilog project - Evaluation.

4. Test 1 - VHDL/Verilog, Verilog/SystemVerilog project - Assignment.

5. Verilog/SystemVerilog project - Consultation.

6. Test 2 - Verilog/SystemVerilog, Verilog/SystemVerilog project - Evaluation.

Study Objective:

The goal of the course is to acquaint students with the properties of the above-mentioned languages and their use for verification (simulation).

Study materials:

Mehta, A. B. : SystemVerilog Assertions and Functional Coverage: Guide to Language, Methodology and Applications. Springer, 2016. ISBN 9783319305394.

Mehta, A. B. : ASIC/SoC Functional Design Verification: A Comprehensive Guide to Technologies and Methodologies. Springer, 2018. ISBN 9783319594187.

Mehler, R. : Digital Integrated Circuit Design Using Verilog and Systemverilog (1st Edition). Elsevier, 2014. ISBN 9780124095298.

Cohen, B. - Kumari, S. V. A. - Piper, L. : SystemVerilog Assertions Handbook (3rd Edition). VhdlCohen Publishing, 2013. ISBN 978-0-9705394-3-6.

Note:

Further information:

https://courses.fit.cvut.cz/MI-SIM/

No time-table has been prepared for this course

The course is a part of the following study plans:

• Master specialization Computer Security, in Czech, 2020 (elective course)
• Master specialization Design and Programming of Embedded Systems, in Czech, 2020 (PS)
• Master specialization Computer Systems and Networks, in Czech, 202 (elective course)
• Master specialization Management Informatics, in Czech, 2020 (elective course)
• Master specialization Software Engineering, in Czech, 2020 (elective course)
• Master specialization System Programming, in Czech, version from 2020 (elective course)
• Master specialization Web Engineering, in Czech, 2020 (elective course)
• Master specialization Knowledge Engineering, in Czech, 2020 (elective course)
• Master specialization Computer Science, in Czech, 2020 (elective course)
• Mgr. programme, for the phase of study without specialisation, ver. for 2020 and higher (PS, VO)
• Master Specialization Digital Business Engineering, 2023 (VO)
• Master specialization System Programming, in Czech, version from 2023 (elective course)
• Master specialization Computer Science, in Czech, 2023 (elective course)