Design of Integrated Circuits

Course guarantor:

Jiří Jakovenko

Lecturer:

Dalibor Barri, Jiří Jakovenko

Tutor:

Dalibor Barri, Jiří Jakovenko

Supervisor:

Department of Microelectronics

Synopsis:

Main tasks of integrated circuits designer; design abstraction levels - Y chart. Definitions of specification, feasibility study, criteria for technology and design kits selection. Integrated systems design and simulation methodologies. Floorplanning, place and route, layout, testbenches design and verification.

Requirements:

moodle.fel.cvut.cz

Syllabus of lectures:

|1. Main tasks of analogue and digital integrated circuits designer; design methodologies (top down, bottom up), design abstraction levels - Y chart.

2. Application specific integrated circuits systems types, full custom design, gate array, standard cells, programmable array logic; main features, economical aspect of the design.

3. Full customs integrated systems, feasibility study, specification, criteria for technology and design kits selection.

4. World standards and CAD tools for analog and mix-signal integrated circuits design, design of RF and mobile low power systems.

5. Design tools for automatic generation of analog behavior models, bottom up design methodology, macro blocks.

6. Design principles of mix-signal integrated circuits, purpose of hierarchical design, digital and analogue block interface, CAD design tools for automatic circuit generation; functional and static time analysis, formal verification; Verilog-A, Verilog-AMS, VHDL-A.

7. Design aspects of radiofrequency integrated circuits ( RFIC WLAN), design methodologies, main architectures, technologies, Sectre RF simulator.

8. Design tools and methodologies for digital integrated circuits and systems; language VHDL, Verilog; library cells; parameters extractions for library cells development.

9. Frond end design - functional specification, RTL, logic synthesis, Gate-level netlist, behavioral stimulus extraction.

10. Back End design - specification of Design Kit, mapping of the design, Floorplanning, place and route, layout, parasitic extraction, layout versus schema check (LVS).

11. Methods of physical synthesis, placement of functional blocks, power lines design and distribution, simulation of interconnect continuity, design verification.

12. Distribution of clock signal, calculating of delay, static and dynamic timing analysis.

13. Testing, design of testbenches, design verification methods.

14. Tape out and fabrication, integrated systems verification, scaling and design mapping to different technologies.

Syllabus of tutorials:

1. Introduction of the CDN-SKILL language

2. Semi-ideal Bandgap reference circuit

· theory

· design

· ideal OpAmp + BJT + Res

3. Introduction to OpAmp

· specification

· gm/Id methodology

4. Current Mirror - design

· design

· multiple factor

· output resistance

5. Differential pair

· active load

· simulation

6. Two Stage OpAmp

· theory

· design of the second stage

7. Two Stage OpAmp

· theory

· stability, compensation

8. BGR Design

· theory

· design+simulation

9. Layout of the BGR

· matching, WPE

· current mirror

10. Layout of the BGR

· antenna diode

· differential pair

11. Layout of the BGR

· load + 2nd stage

12. Layout of the BGR

· BJT + RES + OpAmp

13. Check of the tasks, final assessment.

14. one week is off, reserved

Study Objective:

Study materials:

B. Razavi: Design of Analog CMOS Integrated Circuits, McGRAW-Hill, 2001

B. Murari, F. Bertotti, G.A.Vignola: Smart Power ICs, Springer, 2002

P. Gray, P Hurst, s. Lewis, R. Mayer: Analysis and Design of Analog Integrated Circuits, John Wiley and Sons, 2000

Note:

Further information:

https://moodle.fel.cvut.cz/course/view.php?id=2849

Time-table for winter semester 2025/2026:

Time-table is not available yet

Time-table for summer semester 2025/2026:

	06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Wed	roomT2:C3-s143 Barri D. 09:15–10:45 (lecture parallel1) Dejvice roomT2:C3-s143 Barri D. 12:45–14:15 (lecture parallel1) Dejvice roomT2:B2-s141k Jakovenko J. 11:00–12:30 (lecture parallel1) Dejvice
Thu
Fri

The course is a part of the following study plans:

• Electronics and Communications - Electronics (compulsory course in the program)
• Electronics and Communications - Technology of the Internet of Things (compulsory elective course)