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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2022/2023

Digital Engineering

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Code Completion Credits Range Language
BE2B32DIT Z,ZK 4 2P + 2L English
Lecturer:
Michal Lucki (guarantor)
Tutor:
Michal Lucki (guarantor)
Supervisor:
Department of Telecommunications Engineering
Synopsis:

In this course, students will learn design principles for combinational and sequential digital circuits, using TTL components as well as field programmable gate arrays. The functional design using standard mathematical description and VHDL will be used for designing and realization of various digital circuits. The laboratory classes will be arranged as a set of laboratory tasks and practical examples. Some laboratory lessons will be focused on VHDL and its application for realization of basic digital circuits using FPGAs, their simulations and emulations as well as creating more advanced digital blocks.

Requirements:

The prerequisite is the knowledge on basic mathematic operations at the high school level.

Syllabus of lectures:

1. Introduction to FPGA and VHDL. Simulation and HW implementation. First project on FPGA.

2. Boolean algebra, logical gates and functions. Truth tables. Karnaugh maps. Binary number system.

3. Combinational logic circuits (Boolean expression). Circuits with hysteresis and feedback loop. Selected circuits - full adder.

4. VHDL syntax - program structure, ports, architecture, variables. Boolean expression and behavioral design in VHDL.

5. Hardware and software platforms for VHDL. Creating a project in Xilinx Spartan vs. Notepad++/GHDL/GTKWave.

6. Processes and signals in VHDL. Sequential vs. concurrent statements in VHDL. Case-when, if-elsif, with-select instructions in VHDL. Concatenation of variables. Vectors.

7. Static and dynamic hazard. Selected functional blocks. Decoder, 3-state logic, multiplexer.

8. Mid-term test.

9. Public holiday – no classes.

10. RS latch, D and JK flip-flops. VHDL - working with clock.

11. Synchronous sequential finite state Moore machine. Transient and output functions.

12. Solving tasks (locking system, coffee machine, delaying circuit for bubls). Case studies in VHDL.

13. Sequential Mealy machine. Modulo counters, frequency dividers, shift registers. Universal model of a Mealy machine in VHDL.

14. Spare week, recapitulation.

Syllabus of tutorials:

1. Introduction, introduction into laboratory tasks, conditions for credits.

2. Number systems, arithmetical operations in number systems.

3. Boolean algebra, logic functions, expression of logic functions.

4. Karnaugh maps. Minimization and implementation of logic functions.

5. Combinational logic circuits - design and implementation on FPGA (Schematics).

6. Multiplexers - design and implementation.

7. Test 1. Designing combinational logic circuits.

8. Sequential logic circuits, case studies.

9. Basic blocks in VHDL, modules, ports, signals.

10. RS-latch, D-type flip-flop. Binary adders.

11. Simulation of combinational circuits using VHDL.

12. Simulation of sequential circuits using VHDL.

13. Test II. Designing sequential logic circuits.

14. Assessment, credits.

Study Objective:

The goal of this course is to introduce combinational and sequential logic circuits implemented on TTL compoments as well as modern field programmable gate arrays programmed in VHDL.

Study materials:

[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets (IEEE Press Understanding Science & Technology Series), 1998

[2] CHU, PONG P.: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience; 1 edition, 2008

[3] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, 2010

[4] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, 2011

[5] WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer Science), 2010

[6] FABRICIUS, E.: Digital Design and Switching Theory CRC Press; 1 edition, 1992

Note:
Further information:
https://moodle.fel.cvut.cz/courses/BE2B32DIT
Time-table for winter semester 2022/2023:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomT2:B3-703
Lucki M.
14:30–16:00
(lecture parallel1)
Dejvice
Laboratoř K132
roomT2:B3-703
Lucki M.
16:15–17:45
(lecture parallel1)
Dejvice
Laboratoř K132
roomT2:B3-703
Lucki M.
18:00–19:30
(lecture parallel1)
Dejvice
Laboratoř K132
Wed
Thu
Fri
Time-table for summer semester 2022/2023:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2022-09-29
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