Digital Technique
| Kód | Zakončení | Kredity | Rozsah | Jazyk výuky |
|---|---|---|---|---|
| BE2B32DIT | Z,ZK | 4 | 2P + 2L | anglicky |
- Garant předmětu:
- Michal Lucki
- Přednášející:
- Michal Lucki
- Cvičící:
- Michal Lucki, Tomáš Straka
- Předmět zajišťuje:
- katedra telekomunikační techniky
- Anotace:
-
In this course, students will learn design principles for combinational and sequential digital circuits, using TTL components as well as field programmable gate arrays. The functional design using standard mathematical description and VHDL will be used for designing and realization of various digital circuits. The laboratory classes will be arranged as a set of laboratory tasks and practical examples. Some laboratory lessons will be focused on VHDL and its application for realization of basic digital circuits using FPGAs, their simulations and emulations as well as creating more advanced digital blocks.
- Požadavky:
-
The prerequisite is the knowledge on basic mathematic operations at the high school level.
- Osnova přednášek:
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1. Boolean algebra, logic gates and functions. Truth tables. K-maps.
2. Introduction to FPGA and VHDL. Simulation and HW implementation.
3. Creating a project – a digital process in GHDL.
4. Combinational logic circuits (Boolean expression). Circuits with hysteresis. Multiplexers.
5. VHDL design - program structure, ports, architecture, variables. Boolean expression.
6. Processes in VHDL. Case-when, if-elsif, with-select statements in VHDL. Vectors.
7. Static and dynamic hazard. Selected functional blocks. Decoder, 7-segment display.
8. Mid-term test - circuit design and VHDL.
9. RS latch, D and JK flip-flops. VHDL - working with clock.
10. Synchronous sequential finite state Moore machine. Transient and output functions.
11. Case studies: locking system, coffee machine, delaying circuit.
12. Sequential Mealy machine. Modulo counters.
13. Final test – circuit design, VHDL.
14. Spare week, retakes.
- Osnova cvičení:
-
1. Boolean algebra, logic gates and functions. Truth tables. K-maps.
2. Introduction to FPGA and VHDL. Simulation and HW implementation.
3. Creating a project in GHDL (two-bit adder).
4. Combinational logic circuits - analytic design.
5. VHDL design using Boolean expression.
6. Processes in VHDL. Case-when, if-elsif, with-select statements in VHDL. Vectors.
7. Modelling more advanced combinational functional blocks in VHDL.
8. Mid-term test - circuit design and VHDL.
9. RS latch, D and JK flip-flops. VHDL - working with clock.
10. Synchronous sequential finite state Moore machine - analytic design.
11. Case studies: locking system, coffee machine, delaying circuit.
12. Sequential Mealy machine in VHDL. Modulo counters.
13. Final test – circuit design, VHDL.
14. Spare week, retakes.
- Cíle studia:
-
The goal of this course is to introduce combinational and sequential logic circuits implemented on TTL compoments as well as modern field programmable gate arrays programmed in VHDL.
- Studijní materiály:
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[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets (IEEE Press Understanding Science & Technology Series), 1998
[2] CHU, PONG P.: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience; 1 edition, 2008
[3] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, 2010
[4] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, 2011
[5] WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer Science), 2010
[6] FABRICIUS, E.: Digital Design and Switching Theory CRC Press; 1 edition, 1992
- Poznámka:
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2 lectures + 2 exercises
- Další informace:
- https://moodle.fel.cvut.cz/courses/BE2B32DIT
- Rozvrh na zimní semestr 2024/2025:
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06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po Út St Čt Pá - Rozvrh na letní semestr 2024/2025:
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06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po Út St Čt Pá - Předmět je součástí následujících studijních plánů: