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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Architectures of Computer Systems

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Code Completion Credits Range Language
BI-APS.1 Z,ZK 5 2P+2C Czech
Lecturer:
Michal Štepanovský
Tutor:
Dana Čermáková, Michal Šoch, Michal Štepanovský, Yelena Trofimova
Supervisor:
Department of Computer Systems
Synopsis:

Students understand architectures of uniprocessor computers at the level of machine instructions, with emphasis to instruction pipelining and memory hierarchy. They know the main concepts of RISC and CISC architectures. They learn how modern computers work and how they are constructed. They learn about the techniques that today's processors use to increase the program execution speed. They have a basic knowledge allowing them to optimise their programs to fully exploit a given processor architecture. They get an idea about the trends in the area of computer architectures and how they will affect software. They also understand the architectures of vector processors, their use in today's microprocessors. They understand the principles of shared-memory multiprocessor system architectures and the issues of memory consistency.

Requirements:

Basic knowledge of combinational and sequential logical circuits. Knowledge of basic instruction cycle and assembly labguage programming. Programing in C, the role of a compiler for a higher level PL.

Syllabus of lectures:

1. Quantitative principles of computer design

2. Instruction Set Architecture (ISA)

3. Introduction to Verilog

4. Single-cycle RISC processor design

5. Pipelined RISC processor design

6. Memory hierarchy: cache memory

7. Memory hierarchy: virtual memory

8. Coherence of shared memory in multiprocessor systems

9. Memory consistency and synchronization primitives

10. Superscalar processors I

11. Superscalar processors II

12. Superscalar processors III

Syllabus of tutorials:

1. Evaluation of computer performance

2. ISA and the MIPS assembly language

3. Programming in assembly language for MIPS

4. Hardware description language (Verilog)

5. Basic components of simple RISC processors

6. Pipelined processor

7. Cache memory viewed by CPU/assembler

8. Cache memory viewed by a C/C++ programmer

9. MESI coherence protocol

10. Memory consistency and synchronization primitives

11. Memory consistency viewed by a C/C++ programmer

12. Superscalar processors

13. Semestral projects check, assessment

Study Objective:

Not translated

Study materials:

[1] Patterson, D. A. - Hennessy, J. L.: Computer Organization and Design: The Hardware/Software Interface, 4th Edition, Morgan Kaufmann, 2011, 978-0123747501,

[2] Hennessy, J. L. - Patterson, D. A.: Computer Architecture: A Quantitative Approach, 5th Edition, Morgan Kaufmann, 2011, 978-0123838728.

Note:
Further information:
https://courses.fit.cvut.cz/BI-APS/
Time-table for winter semester 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomTH:A-s134
Štepanovský M.
09:15–10:45
(lecture parallel1)
Thákurova 7 (FSv-budova A)
As134
Tue
Fri
roomTH:A-1042
Štepanovský M.
14:30–16:00
(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
roomTH:A-1042
Štepanovský M.
16:15–17:45
(lecture parallel1
parallel nr.102)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
Thu
roomTH:A-1042
Štepanovský M.
11:00–12:30
(lecture parallel1
parallel nr.103)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
roomTH:A-1042
Štepanovský M.
12:45–14:15
(lecture parallel1
parallel nr.104)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
Fri
Time-table for summer semester 2019/2020:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-09-23
For updated information see http://bilakniha.cvut.cz/en/predmet3458406.html