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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Seminars on Digital Design

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Code Completion Credits Range
PI-SCN ZK 4 2+1
Lecturer:
Petr Fišer (guarantor)
Tutor:
Petr Fišer (guarantor)
Supervisor:
Department of Digital Design
Synopsis:

This subject deals with problems of realization and implementation of digital circuits - both combinational and sequential. Basic means of description of digital circuits and basic logic synthesis and optimization algorithms are described. Basics of EDA (Electronic Design Automation) systems are given, together with combinatorial problems emerging in EDA.

Requirements:

Digital system design master courses knowledge.

Syllabus of lectures:

1. Representations of logic functions

2. Binary decision diagrams (BDDs), structures derived from

3. Other representations of logic functions and digital circuits

4. Two-level minimization

5. Multi-level logic synthesis, decomposition - algebraic methods

6. Multi-level logic synthesis, decomposition - Boolean methods

7. Exploiting don't cares in multi-level logic synthesis and optimization

8. Sequential circuits synthesis. Automata theory. Decomposition, automata realization. Sequential circuits optimization

9. Asynchronous circuits

10. Technology mapping, timing models

11. Contemporary synthesis - ABC

12. Combinatorial problems in EDA systems

Syllabus of tutorials:

1. Binary decision diagrams (BDDs)

2. Two-level functions descriptions. PLA. Espresso and other two-level minimizers

3. Multi-level functions descriptions. Blif. Logic synthesis and optimization tool SIS

4. Logic synthesis and optimization tool ABC

5. SAT problem, solvers. Circuit-SAT conversion

6. Equivalence checking

Study Objective:

This subject will extend practical and theoretical skills obtained from „PCS“ and „NPVS“ master courses by recent and new trends in digital design field of research and practice.

Study materials:

G. D. Hachtel, F. Somenzi: „Logic Synthesis and Verification Algorithms“, Kluwer Academic Pub, 1996, 564 p.

S. Hassoun, T. Sasao, „Logic Synthesis and Verification“, Boston, MA, Kluwer Academic Publishers, 2002, 454 p.

Proceedings of conferences of digital design, e.g. DAC, DATE, DDECS, DSD, ISWBP, etc.

Note:
Time-table for winter semester 2018/2019:
Time-table is not available yet
Time-table for summer semester 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
roomT9:343
Fišer P.
12:45–14:15
(lecture parallel1)
Dejvice
NBFIT učebna
roomT9:343
Fišer P.
14:30–16:00
EVEN WEEK

(lecture parallel1
parallel nr.101)

Dejvice
NBFIT učebna
Thu
Fri
The course is a part of the following study plans:
Data valid to 2019-07-22
For updated information see http://bilakniha.cvut.cz/en/predmet1602506.html