Logo ČVUT
ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2018/2019

Digital Technique

Přihlášení do KOSu pro zápis předmětu Zobrazit rozvrh
Kód Zakončení Kredity Rozsah Jazyk výuky
BE2B32DIT Z,ZK 4 2+2l
Přednášející:
Michal Lucki (gar.), Pavel Lafata
Cvičící:
Michal Lucki (gar.), Petr Hampl, Pavel Lafata, Tomáš Pehnelt
Předmět zajišťuje:
katedra telekomunikační techniky
Anotace:

In this course, students will learn design principles for combinational and sequential digital circuits, using TTL components as well as field programmable gate arrays. The functional design using standard mathematical description and VHDL will be used for designing and realization of various digital circuits. The laboratory classes will be arranged as a set of laboratory tasks and practical examples. Some laboratory lessons will be focused on VHDL and its application for realization of basic digital circuits using FPGAs, their simulations and emulations as well as creating more advanced digital blocks.

Požadavky:

The prerequisite is the knowledge on basic mathematic operations at the high school level.

Osnova přednášek:

1. Number systems (binary, hexadecimal). Unsigned and signed binary numbers. Binary addition, subtraction, and multiplication. Binary codes - BCD, Gray code.

2. Digital circuits. Boolean Algebra, logic functions. Algebraic minimization of logical functions. De Morgan Transformations. Truth tables. Logic gates.

3. Minimization of logic functions, de Morgan transformations, Karnaugh maps, implementation of logic functions using gates. Static and dynamic hazard.

4. Combinational logic circuits. Design stages. Possibilities to solve sequential logic as combinational circuit with the feedback loop.

5. Multiplexer, demultiplexer. Using 4-bit and 8-bit multiplexers from the TTL series.

6. Equality comparator, priority encoder. 3-state function. Decoder using a „3-state function“.

7. Basic features of VHDL syntax - program structure, ports, architecture, processes, sensitivity lists, objects, and signals.

8. Sequential circuits. Finite state machine. Synchronous Moore machine. Transient and output functions. State diagram and transitions table. Hardware implementation.

9. Latching, switching and memory components. Asynchronous and synchronous operation. RS latch NOR and NAND implementation. D-latch, D-type flip-flop, JK and T flip-flops. Output and transient functions for the memory components.

10. Asynchronous sequential Mealy machine. Automatic regulation. Minimization of transition tables using triangle table. Non-contradicting states.

11. More advanced sequential logics - binary counters, modulo counters, shift registers - design stages.

12. Technologies for HW realization of logic gates and circuits - TTL, CMOS

13. VHDL - simulations, behavioral design, implementation of combinational and sequential machines in Xilinx environment.

14. Summary for the examination.

Osnova cvičení:

1. Introduction, introduction into laboratory tasks, conditions for credits.

2. Number systems, arithmetical operations in number systems.

3. Boolean algebra, logic functions, expression of logic functions.

4. Karnaugh maps. Minimization and implementation of logic functions.

5. Combinational logic circuits - design and implementation on FPGA (Schematics).

6. Multiplexers - design and implementation.

7. Test 1. Designing combinational logic circuits.

8. Sequential logic circuits, case studies.

9. Basic blocks in VHDL, modules, ports, signals.

10. RS-latch, D-type flip-flop. Binary adders.

11. Simulation of combinational circuits using VHDL.

12. Simulation of sequential circuits using VHDL.

13. Test II. Designing sequential logic circuits.

14. Assessment, credits.

Cíle studia:

The goal of this course is to introduce combinational and sequential logic circuits implemented on TTL compoments as well as modern field programmable gate arrays programmed in VHDL.

Studijní materiály:

[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets (IEEE Press Understanding Science & Technology Series), 1998

[2] CHU, PONG P.: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience; 1 edition, 2008

[3] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, 2010

[4] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, 2011

[5] WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer Science), 2010

[6] FABRICIUS, E.: Digital Design and Switching Theory CRC Press; 1 edition, 1992

Poznámka:

2 lectures + 2 exercises

Další informace:
https://moodle.fel.cvut.cz/BE2B99DIT
Rozvrh na zimní semestr 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po
Út
St
místnost T2:B3-703
Lucki M.
09:15–10:45
(přednášková par. 1)
Dejvice
Laboratoř K132
místnost T2:B3-700
Lucki M.
11:00–12:30
(přednášková par. 1)
Dejvice
Laboratoř K132
Čt

Rozvrh na letní semestr 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po
Út
St
Čt
místnost T2:B3-703
Lucki M.
09:15–10:45
(přednášková par. 1)
Dejvice
Laboratoř K132
místnost T2:B3-703
Lucki M.
11:00–12:30
(přednášková par. 1)
Dejvice
Laboratoř K132

Předmět je součástí následujících studijních plánů:
Platnost dat k 25. 4. 2019
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