Logo ČVUT
ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2017/2018

Computer Systems Structures

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah Jazyk výuky
BE5B35SPS Z,ZK 6 3+2L
Přednášející:
Cvičící:
Předmět zajišťuje:
katedra řídicí techniky
Anotace:

The subject introduces into basic hardware structures of computer systems, into their design and architecture. It explains technical background of classic computer systems but also special computer for digital and logic control.

Výsledek studentské ankety předmětu je zde: http://www.fel.cvut.cz/anketa/aktualni/courses/AE0B35SPS

Požadavky:

Boolean algebra, logic circuits

Stránky předmětu: https://moodle.dce.fel.cvut.cz/

Osnova přednášek:

1. Synthesis of combinational logic circuits. Hazards in logic circuits.

2. Introduction into HDL languages for design of circuits for computers

3. Minimization of logic functions. Combinational circuits used in computers - multiplexors, demultiplexors, decoders, comparators, adders. Their descriptions in HDL language.

4. Programmable logic circuits PLD, GAL, iPLSI, XILINX. Their descriptions in HDL language.

5. Event driven systems and finite automaton as its mathematical model. Design and minimization of synchronous and asynchronous automata.

6. Sequential logic systems. Synthesis of asynchronous sequential systems as combinational circuits with feedback. RS, JK a D circuits.

7. Synthesis of sequential logic circuits with clock and circuits used in computers: binary and decade counters, Gray counters, shift registers, interrupt controllers. Examples of HDL descriptions.

8. From automata to processors. Fix and programmable controller. Automaton with micro program. Microprocessor. Instruction cycles. Classic architecture of CPU, bus, memory. von Neumannova, Harvard and modified Harvard architecture.

9. Structure of CPU, data and address registers, counter of instructions, stack pointer, types of instructions, address modes in linear addres space.

10. Machine code of general processor. Basic instructions.

11. Structure and hierarchy of memory: Cache as an associative memory, operational memory, secondary memories (hard drives), fragmentation of memory. Reliability of memories.

12. Interrupts and exceptions. Sources of interrupts, external interrupts, interrupt vectors, interrupts from timers, interrupts generated by CPU and controllers of memory bus.

13. Different width of addresses generated by CPU and physical memory. Mapping of memory, paging, segmentation. Protection of memory, DMA transfers.

14. Differences of industrial programmable controlles (PLC) from classic computers: Structer of PLCs, their properties and methods of programming.

Osnova cvičení:

1. Introduction, safety rules in laboratory, organization.

2. Minimization of maps, demonstration of design in HDL language.

3. Design in HDL, part II.

4. Examples of HDL uses and programming of PLD circuits.

5. Independent work - design of counter.

6. Independent work - Code lock.

7. Written test.

8. Design of controllers and its description in HDL language.

9. Independent work - Simple automaton I.

10. Independent work - Simple automaton II.

11. Independent work - Small controller I.

12. Independent work - Small controller II.

13. Independent work - Small controller III.

14. Credits. Tests repetitions.

Cíle studia:

Introduction into computers systems and basic constructions of computers peripherials.

Studijní materiály:

1. Mano, M. Morris: Digital Design, 4/E, Prentice Hall 2007, ISBN-10: 0131989243

2. Sasao, Tsutomu: Switching Theory for Logic Synthesis, Springer 1999, 376 p., Hardcover, ISBN: 978-0-7923-8456-4

3. Hachtel, G. D., Somenzi, F., Logic Synthesis and Verification Algorithms, Kluwer Academic. 1996.

4. DeMicheli G., Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.

5.P. Ashar, S.Devadas, and A.R. Newton, Sequential Logic Synthesis, Kluwer Academic Publishers, Boston, 1992, Chapters 3 - 5.

Poznámka:

Rozsah výuky v kombinované formě studia: 21p+6l

Další informace:
https://moodle.dce.fel.cvut.cz/course/view.php?id=5
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 23. 11. 2017
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet4357506.html