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STUDIJNÍ PLÁNY
2019/2020

Integrated Systems Design

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah Jazyk výuky
AE2M34NIS Z,ZK 5 2P+2C česky
Přednášející:
Cvičící:
Předmět zajišťuje:
katedra mikroelektroniky
Anotace:

Main tasks of integrated circuits designer; design abstraction levels - Y chart. Definitions of specification, feasibility study, criteria for technology and design kits selection. Integrated systems design and simulation methodologies. Main features of full custom design, gate array, standard cells, programmable array logic. Design aspects of RF and mobile low power systems. Verilog-A, Verilog-AMS, VHDL-A. Logic and physical synthesis. Frond End and Back End design. Floorplanning, place and route, layout, parasitic extraction, time analysis, testbenches design and verification.

Výsledek studentské ankety předmětu je zde: http://www.fel.cvut.cz/anketa/aktualni/courses/AE2M34NIS

Požadavky:

https://moodle.kme.fel.cvut.cz/moodle/login/index.php?lang=cs

Osnova přednášek:

1.Main tasks of analogue and digital integrated circuits designer; design methodologies (top down, bottom up), design abstraction levels - Y chart.

2.Application specific integrated circuits systems types, full custom design, gate array, standard cells, programmable array logic; main features, economical aspect of the design.

3.Full customs integrated systems, feasibility study, specification, criteria for technology and design kits selection.

4.World standards and CAD tools for analog and mix-signal integrated circuits design, design of RF and mobile low power systems.

5.Design tools for automatic generation of analog behavior models, bottom up design methodology, macro blocks.

6.Design principles of mix-signal integrated circuits, purpose of hierarchical design, digital and analogue block interface, CAD design tools for automatic circuit generation; functional and static time analysis, formal verification; Verilog-A, Verilog-AMS, VHDL-A.

7.Design aspects of radiofrequency integrated circuits ( RFIC WLAN), design methodologies, main architectures, technologies, Sectre RF simulator.

8.Design tools and methodologies for digital integrated circuits and systems; language VHDL, Verilog; library cells; parameters extractions for library cells development.

9.Frond end design - functional specification, RTL, logic synthesis, Gate-level netlist, behavioral stimulus extraction.

10.Back End design - specification of Design Kit, mapping of the design, Floorplanning, place and route, layout, parasitic extraction, layout versus schema check (LVS).

11.Methods of physical synthesis, placement of functional blocks, power lines design and distribution, simulation of interconnect continuity, design verification.

12.Distribution of clock signal, calculating of delay, static and dynamic timing analysis.

13.Testing, design of testbenches, design verification methods.

14.Tape out and fabrication, integrated systems verification, scaling and design mapping to different technologies.

Osnova cvičení:

1.CADENCE design system

2.CMOS Design kit description, library cells

3.Demonstration of mix-signal design - hierarchical structuring, design cells abstraction.

4.Demonstration of mix-signal design - simulations, interface definition, Spectre AMS simulator.

5.Demonstration of mix-signal design - corner analysis.

6.Analogue layout, parasitic extraction, design rule check.

7.Digital layout (Back End design), Floorplanning, routing, timing analysis.

8.Student project - design of mix-signal IC.

9.Student project - design of mix-signal IC.

10.Student project - design of mix-signal IC.

11.Student project - design of mix-signal IC.

12.Student project - design of mix-signal IC.

13.Student project - design of mix-signal IC.

14.Student project presentation, final assessment.

Cíle studia:
Studijní materiály:

Michael Smith: Application-Specific Integrated Circuits, Addison-Wesley, 1998

P. Gray, P Hurst, s. Lewis, R. Mayer: Analysis and Design of Analog Integrated Circuits, John Wiley and Sons, 2000

E. Sinencio, A. Andreou: Low-Voltage/Low-Power Integrated Circuits and Systems, John Wiley and Sons, 1998 Mark Zwolinski : Digital System Design and VHDL , Prentice-Hall, 2000

Poznámka:
Další informace:
https://moodle.fel.cvut.cz/enrol/index.php?id=2075
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 15. 9. 2019
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet12810904.html