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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2022/2023
UPOZORNĚNÍ: Jsou dostupné studijní plány pro následující akademický rok.

Architectures of Computer Systems

The course is not on the list Without time-table
Code Completion Credits Range Language
BIE-APS.1 Z,ZK 5 2P+2C English
Garant předmětu:
Pavel Tvrdík
Lecturer:
Pavel Tvrdík
Tutor:
Michal Štepanovský
Supervisor:
Department of Computer Systems
Synopsis:

Students will learn the construction principles of internal architecture of computers with universal processors at the level of machine instructions. Special emphasis is given on the pipelined instruction processing and on the memory hierarchy. Students will understand the basic concepts of RISC and CISC architectures and the principles of instruction processing not only in scalar processors, but also in superscalar processors that can execute multiple instructions in one cycle, while ensuring the correctness of the sequential model of programs. The course further elaborates the principles and architectures of shared memory multiprocessor and multicore systems and the memory coherence and consistency in such systems.

Requirements:

Basic knowledge of combinational and sequential logical circuits. Knowledge of basic instruction cycle and assembly labguage programming. Programing in C, the role of a compiler for a higher level PL.

Syllabus of lectures:

1. Quantitative principles of computer design

2. Instruction Set Architecture (ISA)

3. Introduction to Verilog

4. Single-cycle RISC processor design

5. Pipelined RISC processor design

6. Memory hierarchy: cache memory

7. Memory hierarchy: virtual memory

8. Coherence of shared memory in multiprocessor systems

9. Memory consistency and synchronization primitives

10. Superscalar processors I

11. Superscalar processors II

12. Superscalar processors III

Syllabus of tutorials:

1. Evaluation of computer performance

2. ISA and the MIPS assembly language

3. Programming in assembly language for MIPS

4. Hardware description language (Verilog)

5. Basic components of simple RISC processors

6. Pipelined processor

7. Cache memory viewed by CPU/assembler

8. Cache memory viewed by a C/C++ programmer

9. MESI coherence protocol

10. Memory consistency and synchronization primitives

11. Memory consistency viewed by a C/C++ programmer

12. Superscalar processors

13. Semestral projects check, assessment

Study Objective:

Students understand architectures of uniprocessor computers at the level of machine instructions, with emphasis to instruction pipelining and memory hierarchy. They know the main concepts of RISC and CISC architectures. They learn how modern computers work and how they are constructed. They learn about the techniques that today's processors used to increase the program execution performance. They get basic knowledge allowing them to optimize their programs to fully exploit a given processor microarchitecture. They get an idea about the trends in the area of computer architectures and how they will affect software. They understand the principles of shared-memory multiprocessor system architectures and issues of memory consistency.

Study materials:

[1] Patterson, D. A. - Hennessy, J. L.: Computer Organization and Design: The Hardware/Software Interface, 4th Edition, Morgan Kaufmann, 2011, 978-0123747501,

[2] Hennessy, J. L. - Patterson, D. A.: Computer Architecture: A Quantitative Approach, 5th Edition, Morgan Kaufmann, 2011, 978-0123838728.

Note:
Further information:
https://courses.fit.cvut.cz/BIE-APS/
No time-table has been prepared for this course
The course is a part of the following study plans:
Data valid to 2023-06-05
Aktualizace výše uvedených informací naleznete na adrese https://bilakniha.cvut.cz/en/predmet3464506.html