Computer Units
| Kód | Zakončení | Kredity | Rozsah | Jazyk výuky |
|---|---|---|---|---|
| BIE-JPO.21 | Z,ZK | 5 | 2P+2C | anglicky |
- Garant předmětu:
- Pavel Kubalík
- Přednášející:
- Pavel Kubalík
- Cvičící:
- Pavel Kubalík
- Předmět zajišťuje:
- katedra číslicového návrhu
- Anotace:
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Students deepen their basic knowledge of digital computer units acquired in the obligatory course of the program (BIE-SAP), get acquainted in detail with the internal structure and organization of computer units and processors and their interactions with the environment, including accelerating arithmetic-logic units and using appropriate codes for implementation of multiplication. The organization of main memory and other internal memories (addressable, LIFO, FIFO and CAM) will be discussed in detail, including codes for error detection and correction for parallel and serial data transmissions. They will also get acquainted with the methodology of controller design, with the principles of communication of the processor with the environment and the architecture of the bus system. The problems will be practically evaluated in the labs and with the help of the educational microprogrammed processor simulator and programmable hardware design kits (FPGA).
- Požadavky:
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Entry knowledge: Basic knowledge of the structure and architecture of a digital computer, design principles for combinational and sequential circuits, binary arithmetic, the concept of computer memory.
- Osnova přednášek:
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1. Digital computer structure and its functional units.
2. Implementation of arithmetic operations.
3. Circuits for arithmetic operations in 2's complement representation.
4. Design of the CPU control unit and controllers.
5. Circuits for multiplication and division.
6. Architecture and principles of memory elements.
7. Realization of memories with different organization and access (addressable, LIFO, FIFO, CAM).
8. [2] Error-detecting and error-correcting codes for memory data transfers: linear codes.
10. Error-detecting and error-correcting codes for serial data transmissions: cyclic codes.
11. I/O units and their control.
12. Data paths, buses - their types, modes, arbitration.
13. Circuits for floating-point operations.
- Osnova cvičení:
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1. Number systems, conversions and operations.
2. Representations of negative numbers.
3. Simple processor - instructions, machine code, data part.
4. Simple processor - instruction cycle, interface.
5. Simple processor - microprogramming.
6. Simple processor - demonstration of a microprogram.
7. Wired controller design I.
8. Wired controller design II.
9. Linear codes.
10. Cyclic codes.
11. Design of a processor component on FPGA.
12. Demonstration of the designed processor component.
13. Spare seminar, assessment.
- Cíle studia:
-
This module teaches future computer engineers the way how to design their own processors for a specific purpose, what units must be contained in a processor or a computer, and how these units communicate. Everything is demonstrated in hands-on experiments with FPGA and simulators.
- Studijní materiály:
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1. Hennesy, J. L., Patterson, D. A. ''Computer Architecture: A Quantitative Approach (6th Edition)''. Morgan Kaufmann, 2017. ISBN 9780128119051.
2. Tanenbaum, A. S. ''Structured Computer Organization (6th Edition)''. Prentice Hall, 2013. ISBN 9780132916523.
3. Stallings, W. ''Computer Organization and Architecture: Designing for Performance (10th Edition)''. Prentice Hall, 2016. ISBN 9780134101613.
4. Hamacher, C., Vranesic, Z., Zaky, S. ''Computer Organization (5th Edition)''. McGraw-Hill, 2011. ISBN 9781259005275.
- Poznámka:
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Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/BIE-JPO/
Na tento předmět navazuje v magisterském studiu předmět Počítačová aritmetika.
- Rozvrh na zimní semestr 2024/2025:
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06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po Út St Čt Pá - Rozvrh na letní semestr 2024/2025:
- Rozvrh není připraven
- Předmět je součástí následujících studijních plánů: