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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2011/2012

Computer Hardware

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Code Completion Credits Range Language
14Y1HW KZ 2 2+0 Czech
Lecturer:
Vít Fábera
Tutor:
Vít Fábera
Supervisor:
Department of Informatics and Telecommunications
Synopsis:

Common computer architecture, basics of logical circuits design and their realization with help of FPGA. In detail, description of computer structure and separate parts designing - controllers, arithmetic and logic units, I/O subsystem.

Requirements:

basic knowledge of electrotechnics and electronics

Syllabus of lectures:
Syllabus of tutorials:
Study Objective:

Knowledge acquisition concerning computer architecture and function, fundamentals of logical circuits design using programmable gate arrays, communication with peripherals.

Study materials:

Douša J., Jáneš V.: Logické systémy, Praha, lecture notes of ČVUT, 1998

Pluháček A: Návrh logiky počítačů, Praha, lecture notes of ČVUT, 1995

Bokr J., Jáneš V.: Logické systémy, Praha, ČVUT, 1999

Katz R. H: Contemporary Logic Design, The Benjamin/Cummings Publishing Company

Fábera V.: Úvod do hardware počítačů, ČVUT, 2005

Note:
Time-table for winter semester 2011/2012:
Time-table is not available yet
Time-table for summer semester 2011/2012:
Time-table is not available yet
The course is a part of the following study plans:
Generated on 2012-7-9
For updated information see http://bilakniha.cvut.cz/en/predmet24065005.html