Seminars on Digital Design

Lecturer:

Petr Fišer (gar.), Hana Kubátová (gar.)

Tutor:

Petr Fišer (gar.), Hana Kubátová (gar.)

Supervisor:

Department of Digital Design

Synopsis:

This subject deals with the problems of realization and implementation of digital circuits - both combinational and sequential with respect to recent design platforms, programmable circuits and ASIC, timing, optimization and verification.

Requirements:

Digital system design master courses knowledges.

Syllabus of lectures:

1.Digital circuits realization.Technology properties with respect to timing. Timing models. Technology mapping.

2.Combinatorial synthesis. Boolean function representations (BDD, PLA, etc.), properties. Minimization, (bi-)decompositions, algebraic and Boolean methods, exact and heuristic SAT methods.

3.Sequential circuits. Automata theory, equivalence, decomposition, internal state coding. FSM implementation. Synchronous circuits optimization.

4.Combinatorial algorithms in digital design tools (EDA). SAT, ?set cover?, ?max clique?, ?max flow? and other combinatorial problems crucial in EDA and actual research. Exact and heuristic methods. Theorem proving.

5.Electrical level and timing. Signals, noise immunity, reflections. Electro-magnetic compatibility, cross-talks, ground lines disturbances, clock distributions. Metastability, jitter. Analysis of synchronous circuits, clock domains relations, communication between clock domains.

6.EDA systems. Structures, processes, design procedures. Data import and exports. Work flow in special situations.

7.Verification.

8.Model checking, equivalence checking. implicit and explicit models. PSC language. Assertions, libraries of assertions. Mixed verification methods.

Syllabus of tutorials:

Study Objective:

This subject will extend practical and theoretical skills obtained from „PSC“ master courses by recent and new trends in digital design field of research and practice.

Study materials:

G. D. Hachtel, F. Somenzi: „Logic Synthesis and Verification Algorithms“, Kluwer Academic Pub, 1996, 564 p.

S. Hassoun, T. Sasao, „Logic Synthesis and Verification“, Boston, MA, Kluwer Academic Publishers, 2002, 454 p.

Digital design world and Europe conferences, e.g. DDECS, DSD, ISWBP, etc.

Note:

Time-table for winter semester 2011/2012:

Time-table is not available yet

Time-table for summer semester 2011/2012:

Time-table is not available yet

The course is a part of the following study plans:

• Informatics (VO)