Testing and Reliability

Lecturer:

Petr Fišer (gar.)

Tutor:

Petr Fišer (gar.), Martin Daňhel

Supervisor:

Department of Digital Design

Synopsis:

Students gain knowledge about circuit testing and about methods for increasing reliability and security. They will get practical skills to be able to prepare a test set with the help of the intuitive path sensitization and to use an ATPG for automatic test generation. They will be able to design easy testable circuits and systems with built-in-self-test equipment. They will be able to analyze and control reliability and availability of the designed circuits.

Requirements:

Digital IC design and VHDL.

Syllabus of lectures:

1. Introduction to testing of digital circuits, defects, errors, faults, failures.

2. Test generation for combinational circuits, intuitive path sensitization.

3. Boolean difference, the D algorithm.

4. Fault diagnosis, test minimization, ATPG systems.

5. Memory, processor, FPGA, SoC testing.

6. IDDQ testing, testers, analog circuit testing.

7. Design for testability, IEEE 1149 and 1500 standards.

8. Built-in Self Test, test pattern generation, sample and response compression.

9. Reliability models, reliability indicators.

10. Reliability of mantained and redundant systems.

11. Fault-safe systems, totally self-checking circuits.

12. Reliability improving techniques, design of systems with enhanced reliability.

Syllabus of tutorials:

1. 1-3. Test pattern generation and optimization

2. 4-6. Individual project: Fault detection and localisation

3. 7. IEEE 1149 standard application

4. 8-11. Individual project: BIST design

5. 12-13. Individual project: Enhanced reliability system design

Study Objective:

Students will gain an overview about circuit testing and about methods for increasing reliability and security. Students will understand the complexity of fault detection, fault localisation, reliability evaluation and enhancement by solving practical examples and projects. They will be able to optimize the trade-off between introduced redundancy and the measure of testability and security of the proposed system. Students will obtain a competence for getting a position of testing engineer in the teams working on complex digital designs.

Study materials:

1. Novák, O., Gramatová, E., Ubar, R. ''Handbook of testing electronic systems''. Praha: Publishing House of CTU, 2005. ISBN 80-01-03318-X.

Note:

Time-table for winter semester 2011/2012:

	06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri	roomT9:301 Fišer P. 12:45–14:15 (lecture parallel1) Dejvice NBFIT učebnaroomT9:345 Daňhel M. 14:30–16:00 ODD WEEK (lecture parallel1 parallel nr.101) Dejvice NBFIT HW ucebna
Thu
Fri

Time-table for summer semester 2011/2012:

Time-table is not available yet

The course is a part of the following study plans:

• Design of Digital Systems, Version for Students who Enrolled in 2010, Presented in Czech (compulsory course of the specialization)
• Master Informatics, Version for Students who Enrolled in 2010, Presented in Czech (VO)
• Master Informatics, Presented in Czech, Version for Students who Enrolled in 2011 (VO)
• Design of Digital Systems, Presented in Czech, Version for Students who Enrolled in 2011 (compulsory course of the specialization)
• Master Informatics, Presented in Czech, Version for Students who Enrolled in 2012 (VO)
• Design of Digital Systems, Presented in Czech, Version for Students who Enrolled in 2012 (compulsory course of the specialization)