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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2011/2012

Computer Structure and Architecture

The course is not on the list Without time-table
Code Completion Credits Range
YE14SAP Z,ZK 5 2+2s
Lecturer:
Tutor:
Supervisor:
Department of Electric Drives and Traction
Synopsis:

Digital computer units and their structure, function and hardware implementation: ALU, control unit, memory system, inputs, outputs, data storage and transfer.

Requirements:

http://motor.feld.cvut.cz/

course YE14SAP

Syllabus of lectures:

1. Computer organization, units and their interface,

2. Logic functions, combinatorial components, gate level design,

3. Sequential components structure, description and implementation

4. Typical computer combinatorial and sequential components (registers,adders,...),

5. Data representation, format, storage and processing,

6. Fixed and floating point arithmetic operation,

7. Arithmetic function implementation,

8. Computer system structure, interrupt system,

9. Instruction set architecture and machine code,

10. Instruction cycle,

11. Instruction, assembly language, machine code,

12. Computer memory system, MMU, virtual memory,

13. Computer peripherals, bus, DMA controller,

14. CISC and RISC type processors,

Syllabus of tutorials:

1.Logic design CAD tool introduction

2.Combinatorial components design I (gate level)

3.Combinatorial components design II

4.Sequential components realization I

5.Sequential components realization II

6.Mid-term test 1

7.IDE tool introduction

8.Computer system structure, interrupt driven task I

9.Computer system structure, interrupt driven task II

10. ISA - artithmetic operation I

11. ISA - artithmetic operation II

12. Mid-term test 2

13. Assesment

Study Objective:
Study materials:

1. Course YE14SAP lectures

2. Mano, M.M.- Ciletti, M.D.: Digital Design 4ed, Prentice Hall, 2006.

3. Haskell, R.E.- Hanna, D.M.: Introduction to Digital Design Using Digilent

FPGA Boards, LBE Books, 2009.

4. Harris,D.M.-Harris,S.L.: Digital Design and Computer Architecture, Elsevier, 2007.

5. Microchip: PIC18F87J11 Family Data Sheet, 2009.

Note:
Further information:
No time-table has been prepared for this course
The course is a part of the following study plans:
Generated on 2012-7-9
For updated information see http://bilakniha.cvut.cz/en/predmet1365006.html