Multiprocessor Architectures

Lecturer:

Tutor:

Supervisor:

Department of Computer Science and Engineering

Synopsis:

The aim of the course is to give students details on architectures of the state-of-the-art high-performance multiprocessor systems, namely those belonging to the category of parallel and scalable servers. Models of memory coherence and consistency will be explained. SW and HW techniques for their implementation will be given for computers with shared and with distributed memory. Cache coherence protocols for distributed memory systems will be extended to virtual shared memory solutions. Also, HW and SW tools for synchronization operations will be explained, namely the locks and barriers.

Requirements:

Syllabus of lectures:

1. Models for memory coherence and consistency

2. Bus-based cache coherence protocols in shared-memory systems

3. Synchronization locks in shared-memory systems

4. Scalable synchronization locks

5. SW barriers in shared-memory systems

6. SW barriers in distributed-memory systems

7. HW barriers in distributed-memory systems

8. HW and SW techniques for virtual shared memory

9. Directory-based cache-coherence schemes

10. Cache-based cache-coherence schemes

11. Hierarchical cache-coherence schemes

12. Fast communication protocols supporting virtual shared memory

13. Dynamically reconfigurrable clusters of workstations

14. Protocols implementing partial memory consistency

Syllabus of tutorials:

1. SW examples of models of memory coherence and consistency

2. Case studies of bus-based cache-coherence protocols

3. Correctness proof of synchronization locks in shared memory

4. Correctness proof of synchronization distributed locks

5. HW and SW tradeoffs of synchronization lock implementations

6. Correctness proof of SW barriers

7. Comparison of SW and HW implementation of barriers

8. A case study of a directory-based cache-coherence scheme

9. A case study of a cache-based cache-coherence scheme

10. A case study of a hierarchical cache-coherence scheme

11. Implementation tradeoffs of coherence schemes

12. A case study of a communication protocol supporting virtual shared memory

13. A case study of a dynamically reconfigurrable cluster of workstations

14. A case study of an architecture with partial memory consistency

Study Objective:

Study materials:

1. P. Culler et al: Parallel Computer Architecture, Morgan Kaufmann, USA,

ISBN 1-55860-343-3

Note:

Further information:

No time-table has been prepared for this course

The course is a part of the following study plans: