Logo ČVUT
Loading...
CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2011/2012

Computer Units

Login to KOS for course enrollment Display time-table
Code Completion Credits Range
X36JPO Z,ZK 5 2+2c
Lecturer:
Alois Pluháček
Tutor:
Alois Pluháček, Pavel Kubalík
Supervisor:
Department of Computer Science and Engineering
Synopsis:

The course is oriented on internal structure and organization of computer components or processor ones and on interface of the processor with environment. The main memory and other internal memories (addressable, LIFO, FIFO, and CAM) organizations are considered. The organization of ALU is mentioned. The design of the control unit and controllers is presented. Also the basic principles of communication with peripheral devices and buses are discussed.

Requirements:

Students are required to solve semestral project, attend mandatory seminars and labs and pass the exam.

Syllabus of lectures:

1.Organization and structure of von Neumann computers

2.Binary adders, subtractors and shifters

3.Arithmetic and logic unit of simple processor

4.Control unit and controllers; microprogrammed control unit

5.Wired control unit

6.Binary multiplication and division and theirs implementation

7.Floating point representation

8.Basic principles of error detection and correction

9.Linear and cyclic codes

10.Main memory - its possible organization and interface

11.Other internal memories, theirs organization and using - addressable memories, LIFO, FIFO, CAM

12.I/O units and theirs control - DMA, channels and I/O processors

13.Buses - types, modes, and arbitration

14.Spare

Syllabus of tutorials:

1.Number systems, conversions and operations

2.Representations of negative numbers

3.Simple processor - instructions, machine code, data part

4.Simple processor - instruction cycle, interface

5.Simple processor - microprogramming

6.Simple processor - demonstration of microprogramm

7.Wired controller design

8.Multipliers and divisors

9.Floating point representation

10.Design of processor component on FPGA

11.Design of processor component on FPGA

12.Demonstration of designed processor component

13.Control codes

14.Spare and assessment

Study Objective:
Study materials:

1.Hennesy, J.L., Patterson,D.A. Computer Architecture: A Quantitative Approach. San Francisco: Morgan Kaufmann Publishers. 1996

2.Tanenbaum,A.S. Structured Computer Organization. Upper Saddle River: Prentice-Hall. 1999

3.Stallings,W. Computer Organization and Architecture: Designing and Performance. Upper Saddle River: Prentice-Hall. 2000

4.Hamacher,V.C., Vranesic,Z.G, Zaky,S.G. Computer Organization. New York: McGraw-Hill. 1996

Note:
Time-table for winter semester 2011/2012:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
Thu
room

14:30–16:00
(lecture parallel1)
room

18:00–19:30
(lecture parallel1
parallel nr.102)

Fri
Time-table for summer semester 2011/2012:
Time-table is not available yet
The course is a part of the following study plans:
Generated on 2012-7-9
For updated information see http://bilakniha.cvut.cz/en/predmet11607204.html