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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2011/2012

Application of Programmable Circuits 1

The course is not on the list Without time-table
Code Completion Credits Range
31AP1 Z,ZK 4 2+2s
Lecturer:
Tutor:
Supervisor:
Department of Circuit Theory
Synopsis:

Architectures and Application of Programmable Devices is the basic course explaining architecture, function and application of simple programmable logic devices. Students use and extend their knowledge from Circuits Design Techniques in Digital Systems, learn to define logic function in hardware description languages with different design systems and try some individual designs. These designs are verified on hardware kit with GAL and ispLSI devices.

Requirements:
Syllabus of lectures:

1. Introduction, full-custom, semi-custom and user-programmable integrated circuits

2. Programmable circuits characteristics and types, design phases

3. User programmable logic devices - PLD, FPGA

4. Architecture and using of PLD

5. Description of PLD function

6. Hardware description languages, design flow, design systems

7. Methods of design verification and functional check

8. Architecture and usage of Complex PLD

9. Architecture and usage of CPLD isp Lattice

10. Architecture and usage of mother CPLD types

11. Architecture and usage of FPGA XILINX and Actel

12. Programming of PLD and FPGA, programmers, algorithms

13. Device packages

14. New architectures

Syllabus of tutorials:

1. Introduction, full-custom, semi-custom and user-programmable integrated circuits

2. Using of PLD, design flow, design systems, description of PLD function

3. Design phases of PLD, simple PLD design tools

4. Individual work with design systems for PLD, more complex tools

5. Individual work with design systems for PLD

6. Professional design software for PLD circuits

7. Individual task solving with design systems for PLD

8. Individual task solving with design systems for PLD, functional check

9. Individual task solving with design systems for PLD, functional check

10. Individual task solving with design system for CPLD

11. Individual task solving with design system for CPLD, functional check

12. Individual task solving with design system for CPLD, functional check

13. Usage of FPGA XILINX, design system introduction

14. New architectures

Study Objective:
Study materials:

1. Databooks Lattice, Xilinx, Actel, AMD, Philips

2. Web pages with datasheets and tuturials on http://noel.feld.cvut.cz/APO

Note:
Further information:
No time-table has been prepared for this course
The course is a part of the following study plans:
Generated on 2012-7-9
For updated information see http://bilakniha.cvut.cz/en/predmet10998504.html