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ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2011/2012

Computer Structures and Architectures

Přihlášení do KOSu pro zápis předmětu Zobrazit rozvrh
Kód Zakončení Kredity Rozsah Jazyk výuky
BIE-SAP Z,ZK 6 2+3
Přednášející:
Jiří Douša (gar.)
Cvičící:
Petr Fišer (gar.), Jiří Douša (gar.)
Předmět zajišťuje:
katedra číslicového návrhu
Anotace:

Students understand basic digital computer units and their structures, functions, and hardware implementation: ALU, control unit, memory system, inputs, outputs, data storage and transfer. In the labs, students gain practical experience with the design and implementation of the logic of a simple processor using modern digital design tools.

Požadavky:

Basic knowledge of physical principles of digital circuits (transistors as switches, implementation of registers, data storage principles) and fundamentals of discrete mathematics (number representation systems, Boolean algebra).

Osnova přednášek:

1. Introduction, basic architecture of a computer, data representation.

2. Logic functions and their descriptions, combinatorial circuits, implementation using gates.

3. Sequential circuits. Synchronous design, implementation using gates and flip-flops. Mealy and Moore automata.

4. Typical combinatorial and sequential components of a computer, their implementations (encoder, adder, counter, register).

5. Data, its representation and processing.

6. Arithmetic operations with signed numbers. Fix-point and floating point numbers.

7. Implementation of arithmetic operations.

8. Memories - memory cell structure, static and dynamic memories.

9. Memory subsystem of a computer. Peripheral devices.

10. Instructions and machine code.

11. Instruction set architecture, processor design.

12. The SAP processor.

13. Control units, basic types of processors.

Osnova cvičení:

1. Adders, gates, practical implementation.

2. Boolean algebra, minimization, gates.

3. Combinatorial circuits, converters.

4. Minimization, gate-level design, logic functions.

5. Sequential circuits, counter, sequence matching.

6. Sequential design, graph of transitions, table, implementation using D-type flip-flops and gates.

7. Architecture of the AVR processor, sample program.

8. Arithmetics, addition, negative numbers, overflow, complement code.

9. Program - shifts, ASCII.

10. Test, project assignment. Assembler.

11. Project work - display.

12. Arithmetic programs, shifts, control of peripherals.

13. Project result presentations.

Cíle studia:

The module teaches basic knowledge of digital computer construction principles, how a computer performs its operations, what machine code is, and how does it relate to higher programming languages.

Studijní materiály:

1. Douša, J., Pluháček, A.

„Introduction to Computer Systems“. Praha: ČVUT, 2000. ISBN 80-01-02103-3.

2. Gajski, D. D. „Principles of Digital Design“. Prentice Hall, 1996. ISBN 0133011445.

3. Friedman, A. D., Menon, P. R. „Theory and Design of Switching Circuits“. Computer Science Press, 1975. ISBN 0914894528.

4. McCluskey, E. J. „Logic Design Principles“. Prentice-Hall, 1986. ISBN 0135397685.

5. Sasao, T. „Switching Theory for Logic Synthesis“. Springer, 1999. ISBN 0792384563.

6. http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Introductory-Digital-Systems-LaboratoryFall2002/CourseHome/index.htm

Poznámka:

Rozsah=prednasky+proseminare+cviceni2p+1r+2c, Prednasejici: doc. Ing. Hana Kubátová CSc.

Rozvrh na zimní semestr 2011/2012:
Rozvrh není připraven
Rozvrh na letní semestr 2011/2012:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Po
místnost TH:A-1030
Douša J.
12:45–14:15
(přednášková par. 1)
Dejvice
místnost TH:A-1030
Douša J.
14:30–16:00
LICHÝ TÝDEN

(přednášková par. 1
paralelka 101)

Dejvice
Út
St
místnost T9:345
Fišer P.
14:30–16:00
(přednášková par. 1
paralelka 101)

Dejvice
NBFIT HW ucebna
Čt

Předmět je součástí následujících studijních plánů:
Platnost dat k 9. 7. 2012
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet1448306.html