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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Digital Technique

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Code Completion Credits Range Language
B2B32DITA KZ 4 2P + 2L Czech
Lecturer:
Pavel Lafata (guarantor), Daniel Kekrt, Tomáš Zeman
Tutor:
Pavel Lafata (guarantor), Daniel Kekrt, Tomáš Zeman
Supervisor:
Department of Telecommunications Engineering
Synopsis:

The goal of this course is to provide the introduction into designing and realization of digital circuits. First, necessary mathematical apparatus, such as the Boolean algebra, Karnaugh maps, minimization and realization of logical functions is presented, followed by brief introduction into basics of logical circuits, such as the logical gates, flip-flops, TTL and CMOS logic etc. The second part is dedicated mainly to modern designing techniques of digital circuits using programmable FPGA and VHDL language. During these lessons, the basics of VHDL together with numerous examples are evaluated to provide a complex insight into this hardware description language and modern methods of designing and realization of digital circuits.

Requirements:

The only prerequisite is the knowledge of basics of mathematical logic at the high school degree level.

Syllabus of lectures:

1. Number systems with various radices (binary, hexadecimal). Unsigned and signed binary numbers. Binary addition, subtraction, multiplication and division. Modulus and remainder operations, residue number system. Binary codes - BCD, Gray, weighted codes, etc.

2. Logical functions and their expressions, Boolean algebra, logical gates.

3. Minimization of logical functions, algebraic minimization, De Morgan transformations, Karnaugh maps, realization of logical functions using logic gates.

4. Implementation of logical functions and modifications using logical gates, Quine-McCluskey algorithm for minimization of logical functions.

5. Combinational and sequential circuits, logical hazards, synchronous and asynchronous operations, flip-flops, latches.

6. S-R, D, J-K flip-flops, synchronous and asynchronous counters, registers, Moore and Mealy machines.

7. Technologies for HW realization of logic gates and circuits - TTL, CMOS.

8. Modern methods for designing and realization of digital circuits and gates - introduction into programmable devices, FPGA, hardware description languages, VHDL.

9. Basics of VHDL - basic operations, data types, concurrent and sequential domain, conditions, simulations, behavioral design, structural design, flip-flops in VHDL.

10. VHDL language - operators, attributes, conditions, examples of combinational and sequential circuits.

11. Structural description in VHDL language, components, port-map.

12. Sequential circuits in VHDL, loops, counters and frequency dividers.

13. Functions, procedures, packages and libraries in VHDL.

14. Realization of finite state machines in VHDL.

Syllabus of tutorials:

1. Introduction to Digital Engineering, conditions for credits, guidelines for safe work in the laboratory.

2. Numbers with different radices - conversion, basic mathematical operations, calculation of examples.

3. Logical functions, Boolean algebra, minimization of logical functions using Karnaugh maps.

4. Minimization of logical functions using Quine-McCluskey algorithm, conversion between disjunctive and conjunctive function forms.

5. Test.

6. Laboratory task no. 1 - realization of simple logical circuit, hazards in logical circuits, dynamical characteristics of TTL and CMOS.

7. Laboratory task no. 2 - introduction into FPGA and VHDL, realization of code converters using schematic editor in Xilinx iSE.

8. Laboratory task no. 3 - simulations using VHDL, creating testbench in VHDL, simulation of synchronous and asynchronous counters.

9. Laboratory task no. 4 - realization of simple multiplexor in VHDL using conditions.

10. Laboratory task no. 5 - using structural design in VHDL, components, port-mapping.

11. Laboratory task no. 6 - realization of frequency dividers in VHDL.

12. Laboratory task no. 7 - realization of finite state machine in VHDL.

13. Laboratory task - substitutionary lesson.

14. Assessment, credits.

Study Objective:

The goal of this course is to provide the introduction into designing and realization of digital circuits. First, necessary mathematical apparatus, such as the Boolean algebra, Karnaugh maps, minimization and realization of logical functions is presented, followed by brief introduction into basics of logical circuits, such as the logical gates, flip-flops, TTL and CMOS logic etc. The second part is dedicated mainly to modern designing techniques of digital circuits using programmable FPGA and VHDL language. During these lessons, the basics of VHDL together with numerous examples are evaluated to provide a complex insight into this hardware description language and modern methods of designing and realization of digital circuits.

Study materials:

[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets (IEEE Press Understanding Science & Technology Series), 1998

[2] CHU, PONG P.: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience; 1 edition, 2008

[3] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, 2010

[4] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, 2011

[5] WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer Science), 2010

[6] FABRICIUS, E.: Digital Design and Switching Theory CRC Press; 1 edition, 1992

Note:
Further information:
https://moodle.fel.cvut.cz
Time-table for winter semester 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
roomT2:C3-135
Lafata P.
Zeman T.

09:15–10:45
(lecture parallel1)
Dejvice
Posluchárna
roomT2:B3-703
Zeman T.
Kekrt D.

11:00–12:30
(lecture parallel1
parallel nr.101)

Dejvice
Laboratoř K132
roomT2:B3-703
Zeman T.
Kekrt D.

12:45–14:15
(lecture parallel1
parallel nr.102)

Dejvice
Laboratoř K132
roomT2:B3-703
Zeman T.
Kekrt D.

17:00–18:45
(lecture parallel1
parallel nr.103)

Dejvice
Laboratoř K132
Thu
Fri
Time-table for summer semester 2019/2020:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2020-01-24
For updated information see http://bilakniha.cvut.cz/en/predmet5594706.html