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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Digital Technique

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Code Completion Credits Range Language
BD5B32DIT Z,ZK 4 1P + 1L Czech
Lecturer:
Pavel Lafata (guarantor)
Tutor:
Pavel Lafata (guarantor)
Supervisor:
Department of Telecommunications Engineering
Synopsis:

The goal of this course is to provide the introduction into designing and realization of digital circuits. First, necessary mathematical apparatus, such as the Boolean algebra, Karnaugh maps, minimization and realization of logical functions is presented, followed by brief introduction into basics of logical circuits, such as the logical gates, flip-flops, TTL and CMOS logic etc. The second part is dedicated mainly to modern designing techniques of digital circuits using programmable FPGA and VHDL language. During these lessons, the basics of VHDL together with numerous examples are evaluated to provide a complex insight into this hardware description language and modern methods of designing and realization of digital circuits.

Requirements:

The only prerequisite is the knowledge of basics of mathematical logic at the high school degree level.

Syllabus of lectures:

Syllabus:

1. Digital technique, basic terms, number systems, codes.

2. Logic functions, Boolean algebra, logic terms, expressions of logic functions.

3. Minimization of logic functions (truth table, Karnaugh maps, algebraic method), minimization of groups of logic functions.

4. Logic gates based on bipolar and unipolar transistors, characteristics, examples of circuits.

5. Realization of logic functions using given types of gates, logic hazards, eliminations of hazards.

6. Bistable memory circuits: S-R, J-K, T, D, Master-Slave.

7. VHDL language.

8. Memories, types, their characteristics.

9. Multiplexors, decoders, counters, registers, shift registers.

10. Sequential circuits - transition and output functions.

11. Sequential circuits - forms of description, finite state machines.

12. Diagnosis of combinational circuits, basic terms, models.

13. Principles of detection tests.

14. Complete tests, test simplification.

Syllabus of tutorials:

1. Introduction to Digital Engineering, conditions for credits, guidelines for safe work in the laboratory.

2. Numbers with different radices - conversion, basic mathematical operations, calculation of examples.

3. Logical functions, Boolean algebra, minimization of logical functions using Karnaugh maps.

4. Minimization of logical functions using Quine-McCluskey algorithm, conversion between disjunctive and conjunctive function forms.

5. Test.

6. Laboratory task no. 1 - realization of simple logical circuit, hazards in logical circuits, dynamical characteristics of TTL and CMOS.

7. Laboratory task no. 2 - introduction into FPGA and VHDL, realization of code converters using schematic editor in Xilinx iSE.

8. Laboratory task no. 3 - simulations using VHDL, creating testbench in VHDL, simulation of synchronous and asynchronous counters.

9. Laboratory task no. 4 - realization of simple multiplexor in VHDL using conditions.

10. Laboratory task no. 5 - using structural design in VHDL, components, port-mapping.

11. Laboratory task no. 6 - realization of frequency dividers in VHDL.

12. Laboratory task no. 7 - realization of finite state machine in VHDL.

13. Laboratory task - substitutionary lesson.

14. Assessment, credits.

Study Objective:

The goal of this course is to provide the introduction into designing and realization of digital circuits. First, necessary mathematical apparatus, such as the Boolean algebra, Karnaugh maps, minimization and realization of logical functions is presented, followed by brief introduction into basics of logical circuits, such as the logical gates, flip-flops, TTL and CMOS logic etc. The second part is dedicated mainly to modern designing techniques of digital circuits using programmable FPGA and VHDL language. During these lessons, the basics of VHDL together with numerous examples are evaluated to provide a complex insight into this hardware description language and modern methods of designing and realization of digital circuits.

Study materials:

[1] GREGG, J.: Ones and Zeros: Understanding Boolean Algebra, Digital Circuits, and the Logic of Sets (IEEE Press Understanding Science & Technology Series), 1998

[2] CHU, PONG P.: FPGA Prototyping by VHDL Examples: Xilinx Spartan-3 Version, Wiley-Interscience; 1 edition, 2008

[3] PEDRONI, V.: Circuit Design and Simulation with VHDL, MIT Press, 2010

[4] STANKOVIC, R., ASTOLA, J.: From Boolean Logic to Switching Circuits and Automata: Towards Modern Information Technology (Studies in Computational Intelligence), Springer, 2011

[5] WHITESITT, J.: Boolean Algebra and Its Applications (Dover Books on Computer Science), 2010

[6] FABRICIUS, E.: Digital Design and Switching Theory CRC Press; 1 edition, 1992

Note:
Further information:
https://moodle.fel.cvut.cz
Time-table for winter semester 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomT2:B3-703
Lafata P.
14:30–16:00
(lecture parallel1)
Dejvice
Laboratoř K132
roomT2:B3-703
Lafata P.
14:30–16:00
(lecture parallel1)
Dejvice
Laboratoř K132
Fri
room
Lafata P.
09:15–10:45
(lecture parallel1)
roomT2:B3-703
Lafata P.
14:30–16:00
(lecture parallel1)
Dejvice
Laboratoř K132
Thu
Fri
Time-table for summer semester 2019/2020:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2020-05-30
For updated information see http://bilakniha.cvut.cz/en/predmet4975806.html