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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Digital Circuit Simulation

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Code Completion Credits Range
MIE-SIM.16 Z,ZK 5 2+1
Lecturer:
Martin Kohlík (guarantor), Jiří Douša
Tutor:
Martin Kohlík (guarantor)
Supervisor:
Department of Digital Design
Synopsis:

Students gain information regarding the usage of basic tools for the design and simulation of VLSI (very large scale integration) digital circuits (VHDL, Verilog). They also get some knowledge about advanced tools System Verilog & SystemC.

Requirements:

Design methods for combinational and sequential logic circuits, knowledge of number representations, knowledge of the circuit implementations of basic arithmetic operations.

Syllabus of lectures:

1. Fundamental simulation principles, abstraction levels of digital circuit description.

2. [5] VHDL: Entities, architectures, overview of data types and corresponding operations, delta delay, inertial delay, transport delay, sequential environment, signal attributes, resolution function, synthesizable constructs of the language, creating user libraries, data-flow description, blocks, guarded blocks, guarded assignment statements, guarded signals, structural description, configuration of structural architectures, creating tests.

3. [4] Verilog: Analogy with VHDL, modules and their interfaces, overview of data types and operations, sequential environment, nondeterministic Verilog behavior, blocking and nonblocking assignments, parallel environment, nets and strengths, synthesizable constructs of the language, modeling structures, primitive elements, creating tests.

4. [2] Modern trends in the area of digital circuit simulation (transaction level modeling, coverage driven testbench, assertions). SystemC & SystemVerilog: overall characteristic of the system. Methods of parallel simulation.

Syllabus of tutorials:

1. Getting acquainted with the MODELSIM system. Presentation of examples in the VHDL language.

2. Working on the first project.

3. Working on the first project.

4. Working on the second project.

5. Working on the third project.

6. Final evaluation and assessment.

Study Objective:

The goal of the course is to acquaint students with the principles of quasi-parallel simulation of structures, as well as with the properties of the above-mentioned languages and their use for simulation and synthesis.

Study materials:

Dewey, A. M. Analysis and Design of Digital Systems with VHDL. International Thomson Publishing, 1996. ISBN 0534954103.

Cohen, B. VHDL Coding Styles and Methodologies. Springer, 1999. ISBN 0792384741.

Ciletti, M. D. Advanced Digital Design with the Verilog HDL. Prentice Hall, 2002. ISBN 0130891614.

Bhasker, J. A SystemC Primer. Star Galaxy Publishing, 2004. ISBN 0965039129.

Grötker, T., Liao, S., Martin, G., Swan, S. System Design with SystemC. Springer, 2002. ISBN 1402070721.

Note:
Further information:
https://courses.fit.cvut.cz/MIE-SIM/
Time-table for winter semester 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomTH:A-1242
Douša J.
14:30–16:00
(lecture parallel1)
Thákurova 7 (FSv-budova A)
roomTH:A-1048
Kohlík M.
18:00–19:30
EVEN WEEK

(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Servitova laborka
Fri
Thu
Fri
Time-table for summer semester 2018/2019:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-03-25
For updated information see http://bilakniha.cvut.cz/en/predmet4903206.html