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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Logic systems and processors

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Code Completion Credits Range Language
B0B35LSP Z,ZK 6 3P+2L Czech
The course cannot be taken simultaneously with:
Logic systems and processors (BE5B35LSP)
Lecturer:
Richard Šusta (guarantor)
Tutor:
Richard Šusta (guarantor)
Supervisor:
Department of Control Engineering
Synopsis:

The course is an introduction to basic hardware structures of computing resources, their design, and architecture. It provides an overview of the implementation of data operations at hardware and the creation of embedded processor systems with peripherals on advance programmable logic FPGAs.

Requirements:

Boolean algebra, logic circuits

Syllabus of lectures:

1. The structure of computer systems. Logical expressions versus logic gates. Logical cube and build logic functions of Karnaugh maps. Group minimization. Boolean algebra. De Morgan theorem. SAT problem and Shannon expansion. Binary Decision Diagrams.

2nd VHDL language to describe circuits, basic design. Descriptions of basic combinational circuits in the schemes and VHDL.

3. Implementation of basic combinational logic circuits for computers and their descriptions in the schemes and VHDL. Sequential circuits.

4. Sequential circuits and their basic types. Latch-type flip-flops and Master-Slave.

5. Describe in VHDL Behavioral style, registers, and counters.

6. Basic sequential circuits computers. Memory and their structure in VHDL.

7. Implementation of circuits within the FPGA. Problems with the concurrence of parallel operations in logic circuits. Metastability circuit. Elements used in 3rd and 4th project.

8. professional manner for testing and simulation of VHDL programs, ie. Creating Testbench. Using ModelSim simulation breakpoints and stepping in VHDL programs.

9. FSM (Finite State Machine) - genesis, Mealy and Moore automata. Solving machines in VHDL. Tasks leading to FSMs, design and testing machines.

10. From a controller to the processor. Data path. Activity Example 1bitového CPU processor and its testing.

11. The structure of soft-core processor on the chip, its usage and modifications.

12. Processor peripherals and connectivities, internal bus circuits.

13. Advanced CPU and features to build custom embedded systems processor.

14.-Basics interfacing with, or difficulties connecting circuits. Protections of inputs and outputs, problems with the wires, buses and various types of loads. Power Solution and countries. Galvanic isolation.

Syllabus of tutorials:

Students receive credits in practical exercises by solving individual projects on FPGA development boards Altera DE2; which are utilized by dozens of the world's leading universities. License terms for programming the Altera Quartus II environment and allow its installation on the home computer students.

Study Objective:

Introduction into computers systems and basic constructions of computers peripherials.

Study materials:

1. Volnei A. Pedroni: Digital Electronics and Design with VHDL, MORGAN KAUFMANN 2008, ISBN: 0123742706

2. Enoch O. Hwang: Digital Logic and Microprocessor Design with VHDL, Thomson 2006, ISBN: 0-534-46593-5

3. Šusta R.: APOLOS - prerequisite, ČVUT-FEL 2013

Note:
Time-table for winter semester 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomKN:E-23
Šusta R.
12:45–14:15
(lecture parallel1
parallel nr.101)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
14:30–16:00
(lecture parallel1
parallel nr.102)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
17:00–18:45
(lecture parallel1
parallel nr.103)

Karlovo nám.
Laboratoř AB
Fri
roomKN:E-23
Šusta R.
12:45–14:15
(lecture parallel1
parallel nr.104)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
14:30–16:00
(lecture parallel1
parallel nr.105)

Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
17:00–18:45
(lecture parallel1
parallel nr.106)

Karlovo nám.
Laboratoř AB
Thu
roomKN:E-107
Šusta R.
09:15–11:45
(lecture parallel1)
Karlovo nám.
Zengerova posluchárna K1
roomKN:E-23
Šusta R.
15:15–17:00
(lecture parallel1
parallel nr.107)

Karlovo nám.
Laboratoř AB
Fri
Time-table for summer semester 2019/2020:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
Thu
roomKN:E-23
Šusta R.
09:15–11:45
(lecture parallel1)
Karlovo nám.
Laboratoř AB
roomKN:E-23
Šusta R.
12:45–14:15
(lecture parallel1
parallel nr.101)

Karlovo nám.
Laboratoř AB
Fri
The course is a part of the following study plans:
Data valid to 2019-12-12
For updated information see http://bilakniha.cvut.cz/en/predmet4666506.html