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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Design for the FPGA and ASIC Technology

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Code Completion Credits Range Language
MIE-NFA.16 Z,ZK 5 2+1
Lecturer:
Jan Schmidt (guarantor)
Tutor:
Jan Schmidt (guarantor)
Supervisor:
Department of Digital Design
Synopsis:

Students gain the basic knowledge needed to start a career in a design house. They will understand the FPGA and ASIC implementation technologies and the limitations that the technologies impose on the design. They are able to perform and to manage typical workflows, their analytic and synthetic steps, with an emphasis on basic verification. They know the structure and demands of software tools, as well as what to expect from them.

Requirements:

Gates and registers, basic CMOS circuits, simple gate-level design, finite state machine and its synchronous implementation.

Syllabus of lectures:

1. The gist of hardware design. The role and types of decomposition. Synthetic and analytic steps. Basic economy of product design and manufacturing.

2. CMOS circuits, dynamic behavior, power consumption. Technology characterization. Implementation of programmable combinational function and programmable interconnect.

3. Synchronous digital design, timing, models. Clock domains, signal transfer across clock domain boundary. Metastablility.

4. Top-down and bottom-up design process, its steps and iteration loops. Hardware project management, metrics. Intellectual property cores. Reuse methodology.

5. Programmable devices: overview, usage, programming methods. Deployment.

6. FPGA devices: architecture, basic logic blocks, interconnect. Dynamic behavior.

7. FPGA devices: blocks performing computation and communication, memory blocks.

8. Design styles for ASICs. The impact of deep submicron technologies. ASIC design tools.

9. Verification techniques: formal techniques (model checking, equivalence checking), advanced simulation, assertions, hybrid assertion-based techniques.

10. Physical design: routing, placement, technology mapping.

11. Logic synthesis, basic phases, used formalisms. Timing-driven and power-driven synthesis.

12. Behavioral synthesis, areas of use.

13. System-level design, hardware-software decomposition and codesign, design by model refinement.

Syllabus of tutorials:

1. Lab: getting started with equipment, software and kits

2. Lab: synchronous FPGA design

3. Lab: synchronous FPGA design

4. Lab: FPGA design with multiple clock domains

5. Lab: FPGA design with multiple clock domains

6. Lab: FPGA design with multiple clock domains

7. Lab: FPGA design with given speed and external timing

8. Lab: FPGA design with given speed and external timing

9. Lab: FPGA design with given speed and external timing

10. Lab: verification

11. Lab: verification

12. Lab: verification

13. Lab: verification

14. Presentation of results, evaluation

Study Objective:

The module builds a bridge from the basic digital design, which students have learned earlier, to the level where the students will understand professional designers. They will gain insight into the interplay between technology, software tools, workflow, and the quality of the result.

Study materials:

1. Wilson, P. ''Design Recipes for FPGAs''. Newnes, 2007. ISBN 0750668458.

Note:
Time-table for winter semester 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
roomTH:A-1242
Schmidt J.
11:00–12:30
(lecture parallel1)
Thákurova 7 (FSv-budova A)
roomTH:A-1048
Schmidt J.
12:45–14:15
EVEN WEEK

(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Servitova laborka
Tue
Fri
Thu
Fri
Time-table for summer semester 2018/2019:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-03-23
For updated information see http://bilakniha.cvut.cz/en/predmet4659106.html