Logo ČVUT
CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Computer Hardware

The course is not on the list Without time-table
Code Completion Credits Range Language
14W1HW KZ 4 8 Czech
Lecturer:
Tutor:
Supervisor:
Department of Applied Informatics in Transportation
Synopsis:

Design combinational and sequential logical circuits and their implementation on FPGA, VHDL language. Computer architecture, structures of computer components - controller, ALU, memories, I/O subsystem, typical interfaces and buses (PCI Express, I2C, SPI, USB).

Requirements:

Basic knowledge of logical circuits.

Syllabus of lectures:
Syllabus of tutorials:
Study Objective:

Design more complex digital circuits using programmable gate arrays, knowledge acquisition concerning computer architecture and typical interfaces.

Study materials:

Fábera, V.: Úvod do hardware počítačů, skripta ČVUT, 2005

Král, J.: Řešené příklady ve VHDL - Hradlová pole FPGA pro začátečníky, BEN, 2010

Poupa, M., Pinkr, J.: Číslicové systémy a jazyk VHDL, BEN, 2006

Note:
Further information:
No time-table has been prepared for this course
The course is a part of the following study plans:
Data valid to 2019-12-08
For updated information see http://bilakniha.cvut.cz/en/predmet4341206.html