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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Programmable Logic Arrays

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Code Completion Credits Range Language
17PLP ZK 2 2 Czech
Lecturer:
Martin Kropík (guarantor)
Tutor:
Supervisor:
Department of Nuclear Reactors
Synopsis:

Lecture provides information about digital circuits, data representation in digital systems, combinational and sequential/ logic, Boolean algebra, SPLD, CPLD and FPGA chips. Next, lecture is devoted to HDL and VHDL programming languages and development tool ISP Expert Lattice Semiconductors for programming and testing of SPLD and CPLD chips. Finally, students prepare individual design of a CPLD.

Requirements:

-

Syllabus of lectures:

1. Boolean algebra, data representation in digital systems

2. Digital circuits, combinational and sequential logic, asynchronous and synchronous sequential circuits, digital chips of 74XXX types

3. Training course with digital circuits

4. SPLD (simple programmable logical device) circuits, different types, features and internal structure

5. Programming language HDL 1; basic structure, syntax, keywords, simple example

6. Programming language HDL 2, description of logical functions by Boolean equations, truth tables and status automat, testing of designing circuits

7. Programming language HDL 3; examples of SPLD designs with demonstrations

8. CPLD (complex programmable logical device) and FPGA (field-programmable gate array) chips; different types, features and internal structure, comparison with SPLD chips

9. Programming language HDL 4; language features for use with CPLDs, hierarchical structure of designs

10. Programming language VHDL 1; basic features, syntax, keywords, different ways of description of logical functions, comparison with HDL language

11. Programming language VHDL 2; hierarchical structure of design, testing of designs, demonstration of design examples in VHDL

12. - 13. Work on individual CPLD design

Syllabus of tutorials:

Training course with digital circuits, work on individual design of CPLD chip

Study Objective:

Knowledge: knowledge of digital technology, programmable circuits SPLD, CPLD and FPGA, knowledge of circuits design in HDL and VHDL languages

Abilities: orientation in programmable logic, ability to design and test function of circuits

Study materials:

Key references:

ABEL-HDL Reference Manual, Lattice Semiconductor, 2003

D. Perry: VHDL, McGraw Hill, 1998

Getting Started with LabVIEW, National Instruments, 2009

Recommended references:

SPLD, CPLD a FPGA Manuals, webové pages of Lattice Semiconductor a Altera companies

Media and tools:

electronic laboratory of Department of nuclear reactors, HDL and VHDL programming languages

Note:
Time-table for winter semester 2019/2020:
Time-table is not available yet
Time-table for summer semester 2019/2020:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-09-23
For updated information see http://bilakniha.cvut.cz/en/predmet24966105.html