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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Advanced Computer Architectures

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Code Completion Credits Range
PI-VAP ZK 4 0+3
Lecturer:
Tutor:
Pavel Tvrdík (guarantor)
Supervisor:
Department of Computer Systems
Synopsis:

Students will learn the mechanisms for multilevel branch prediction, speculative instruction execution, and speculative data prefetching techniques in ILP processors. The second part is on memory hierarchy systems, memory consistency models, and memory coherence protocols in parallel computer systems with virtual shared distributed memory. The third part is devoted to synchronization mechanisms in parallel systems with distributed memory.

Requirements:

BIE-APS, MIE-PAR, MIE-PAP or equivalents

Syllabus of lectures:

1. Multilevel branch predictors in ILP processors.

2. Speculative instruction execution in ILP processors.

3. Speculative data prefetching techniques in ILP processors.

4. Distributed memoru coherence and consistency models.

5. Memory coherence protocols for virtual shared memory systems.

6. Distributed memory synchronization mechanisms.

Syllabus of tutorials:

No exercises.

Study Objective:

To explain more complex algorithmic and architectural solutions used in modern advanced processors and computers.

Study materials:

Hennessy, J. L., Patterson, D.A.. Computer Architecture: A Quantitative Approach. The Fourth Edition. Morgan Kaufmann, 200X, ISBN 1-55860-724-2.

Shen, J., Lipasti, M.. Modern Processor Design: Fundamentals of Superscalar Processors, McGraw Hill 2005, ISBN 0-07-057064-7.

D. E. Culler, J.P. Singh and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann. ISBN 1-55860-343-3.

Note:
Time-table for winter semester 2018/2019:
Time-table is not available yet
Time-table for summer semester 2018/2019:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-03-25
For updated information see http://bilakniha.cvut.cz/en/predmet1602306.html