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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Computer Units

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Code Completion Credits Range Language
BIE-JPO Z,ZK 5 2+2
Lecturer:
Pavel Kubalík (guarantor)
Tutor:
Pavel Kubalík (guarantor)
Supervisor:
Department of Digital Design
Synopsis:

Students know the internal structure and organization of computer or processor components and their interfacing with the environment. They understand the organization of main memory and other internal memories (addressable, LIFO, FIFO and CAM). They know the organization of an arithmetic unit. They learn the design methodology for control units and controllers, as well as basic principles of communication with peripheral devices and buses. They understand the architecture of a bus system.

Requirements:

Basic knowledge of the structure and architecture of a digital computer, design principles for combinational and sequential circuits, binary arithmetic, principles of computer memory.

Syllabus of lectures:

1. Organization and structure of von Neumann computers.

2. Binary adders, subtractors, and shifters.

3. Arithmetic and logic unit of a simple processor.

4. Control unit and controllers; microprogrammed control unit.

5. Wired control unit.

6. Binary multiplication and division and their implementation.

7. Floating point representation.

8. Basic principles of error detection and correction.

9. Linear and cyclic codes.

10. Main memory - possible organizations and interfaces.

11. Other internal memories, their organization and use - addressable memories, LIFO, FIFO, CAM.

12. I/O units and their control - DMA, channels and I/O processors.

13. Buses - types, modes, arbitration.

Syllabus of tutorials:

1. Number systems, conversions and operations.

2. Representations of negative numbers.

3. Simple processor - instructions, machine code, data part.

4. Simple processor - instruction cycle, interface.

5. Simple processor - microprogramming.

6. Simple processor - demonstration of a microprogram.

7. Wired controller design.

8. Multipliers and dividers.

9. Floating point representation.

10. [2] Design of a processor component on FPGA.

11. Demonstration of the designed processor component.

12. Error detection codes.

Study Objective:

The module teaches future computer engineers the way how to design their own processors for a specific purpose, what units must be contained in a processor or a computer, and how these units communicate. Everything is demonstrated in hands-on experiments with FPGA and simulators.

Study materials:

1. Hennesy, J. L., Patterson, D. A. ''Computer Architecture: A Quantitative Approach, Third Edition''. Morgan Kaufmann, 2002. ISBN 1558605967.

2. Tanenbaum, A. S. ''Structured Computer Organization (5th Edition)''. Prentice Hall, 2005. ISBN 0131485210.

3. Stallings, W. ''Computer Organization and Architecture: Designing for Performance (7th Edition)''. Prentice Hall, 2005. ISBN 0131856448.

4. Hamacher, C., Vranesic, Z., Zaky, S. ''Computer Organization''. McGraw-Hill, 2001. ISBN 0072320869.

Note:
Further information:
https://courses.fit.cvut.cz/BIE-JPO/
Time-table for winter semester 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomTH:A-942
Kubalík P.
09:15–10:45
(lecture parallel1)
Thákurova 7 (FSv-budova A)
Fri
roomTH:A-1042
Kubalík P.
12:45–14:15
(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
Thu
Fri
Time-table for summer semester 2018/2019:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2019-03-22
For updated information see http://bilakniha.cvut.cz/en/predmet1450006.html