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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2018/2019

Computer Structures and Architectures

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Code Completion Credits Range Language
BIE-SAP Z,ZK 6 2P+1R+2C
Lecturer:
Jiří Douša (guarantor)
Tutor:
Petr Fišer, Jiří Douša (guarantor), Peter Guľa, Pavel Kubalík
Supervisor:
Department of Digital Design
Synopsis:

Students understand basic digital computer units and their structures, functions, and hardware implementation: ALU, control unit, memory system, inputs, outputs, data storage and transfer. In the labs, students gain practical experience with the design and implementation of the logic of a simple processor using modern digital design tools.

Requirements:

Basic knowledge of physical principles of digital circuits (transistors as switches, implementation of registers, data storage principles) and fundamentals of discrete mathematics (number representation systems, Boolean algebra).

Syllabus of lectures:

1. Introduction, basic architecture of a computer, data representation.

2. Logic functions and their descriptions, combinatorial circuits, implementation using gates.

3. Sequential circuits. Synchronous design, implementation using gates and flip-flops. Mealy and Moore automata.

4. Typical combinatorial and sequential components of a computer, their implementations (encoder, adder, counter, register).

5. Data, its representation and processing.

6. Arithmetic operations with signed numbers. Fix-point and floating point numbers.

7. Implementation of arithmetic operations.

8. Memories - memory cell structure, static and dynamic memories.

9. Cache memories, virtual memory system.

10. Instructions and machine code.

11. Instruction set architecture, addressing modes.

12. Interrupts, buses.

13. Control units, basic types of processors.

Syllabus of tutorials:

1. Adders, gates, practical implementation.

2. Boolean algebra, minimization, gates.

3. Combinatorial circuits, converters.

4. Minimization, gate-level design, logic functions.

5. Sequential circuits, counter, sequence matching.

6. Sequential design, graph of transitions, table, implementation using D-type flip-flops and gates.

7. Architecture of the AVR processor, sample program.

8. Arithmetics, addition, negative numbers, overflow, complement code.

9. Program - shifts, ASCII.

10. Test, project assignment. Assembler.

11. Project work - display.

12. Arithmetic programs, shifts, control of peripherals.

13. Project result presentations.

Study Objective:

The module teaches basic knowledge of digital computer construction principles, how a computer performs its operations, what the machine code is and how it is related to higher programming languages.

Study materials:

1. Douša, J., Pluháček, A. „Introduction to Computer Systems“. Praha: ČVUT, 2000. ISBN 80-01-02103-3.

2. Gajski, D. D. „Principles of Digital Design“. Prentice Hall, 1996. ISBN 0133011445.

3. Friedman, A. D., Menon, P. R. „Theory and Design of Switching Circuits“. Computer Science Press, 1975. ISBN 0914894528.

4. McCluskey, E. J. „Logic Design Principles“. Prentice-Hall, 1986. ISBN 0135397685.

5. Sasao, T. „Switching Theory for Logic Synthesis“. Springer, 1999. ISBN 0792384563.

6. http://ocw.mit.edu/OcwWeb/Electrical-Engineering-and-Computer-Science/6-111Introductory-Digital-Systems-LaboratoryFall2002/CourseHome/index.htm

Note:
Time-table for winter semester 2018/2019:
Time-table is not available yet
Time-table for summer semester 2018/2019:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
roomTH:A-s135
Douša J.
11:00–12:30
(lecture parallel1)
Thákurova 7 (FSv-budova A)
As135
roomTH:A-s135
Douša J.
14:30–16:00
EVEN WEEK

(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
As135
roomTH:A-1042
Fišer P.
Guľa P.

12:45–14:15
(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
Fri
roomTH:A-1042
Kubalík P.
Guľa P.

09:15–10:45
(lecture parallel1
parallel nr.101)

Thákurova 7 (FSv-budova A)
Hlavickova laborka
Thu
Fri
The course is a part of the following study plans:
Data valid to 2019-05-23
For updated information see http://bilakniha.cvut.cz/en/predmet1448306.html