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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2020/2021

FPGA Applications

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Code Completion Credits Range Language
A0B38APH KZ 5 1P+3L Czech
Lecturer:
Radek Sedláček (guarantor)
Tutor:
Radek Sedláček (guarantor)
Supervisor:
Department of Measurement
Synopsis:

After the short introduction into the structure and technology of programmable circuits (especially the CPLD and FPGA), the lectures are devoted to the VHDL and its usage for simulation and synthesis of digital circuits. Laboratories are focused on CPLD and FPGA circuit applications and on the use of SW instruments for programmable hardware design and simulation. Within the larger project implemented in the second part of laboratories, a complete device (system on the chip) is implemented in the FPGA or CPLD circuit. Students may choose from the list of projects or they can bring their own (even group projects are possible). Development boards with FPGA (or CPLD) are available.

The result of the student survey of the course is here: http://www.fel.cvut.cz/anketa/aktualni/courses/AE0B38APH

Requirements:

Basic knowledge of Boolean algebra, basic logic circuits, and programming in C language

Syllabus of lectures:

1. Programmable components, history, and present.

2. Introduction to VHDL language, design units.

3. Writing numbers of characters and strings.

4. Basic data types and operators.

5. Basic objects - constants, variables, signals.

6. Parallel and sequential domain.

7. Implementation of state machines.

8. Standard libraries, LPM library, and their use.

9. Procedures and functions.

10. Design of combinational and sequential circuits.

11. Tools and methods for simulation.

12. Special internal structures (RAM, PLL, multipliers) and their use.

13. Creation of user libraries.

14. SoC implementation using built-in NIOS II processor.

Syllabus of tutorials:

1. Introduction in QUARTUS II, opening project

2. Logic and arithmetic functions in VHDL, programming in the parallel domain.

3. Programming in the sequential domain - processes, flip-flops, and counters.

4. Design simulation using test vectors and test benches in ModelSim.

5. State automata - variants of VHDL implementation.

6. Usage of internal RAM in projects.

7. Usage of external RAM in projects.

8. Desing of SoC based on NIOS II - example I.

9. Desing of SoC based on NIOS II - example II.

10.Work on project implementation.

11.Work on project implementation.

12.Work on project implementation.

13.Work on project implementation.

14.Final project presentation, assessment.

Study Objective:

The aim of the study is to teach students to understand FPGA circuits from the point of view of their internal structure. Students will learn to program FPGA in VHDL and gain basic knowledge about the design of the so-called system on a chip (SoC). They will also get acquainted with the typical possibilities of using FPGA circuits in practice.

Study materials:

1. Pedroni, V.A.: Digital Electronics and Design with VHDL. Morgan Kaufmann 2008, ISBN: 978-0123742704

2. Ashenden, P. J.: The Designer's guide to VHDL. Morgan Kaufmann 2008. ISBN: 978-0-12-088785-9.

Note:
Further information:
https://moodle.fel.cvut.cz/courses/A0B38APH
Time-table for winter semester 2020/2021:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
roomT2:C4-s150
Sedláček R.
08:15–10:45
(lecture parallel1
parallel nr.101)

Dejvice
Laboratoř MS
roomT2:C4-s150
Sedláček R.
12:45–14:15
ODD WEEK

(lecture parallel1)
Dejvice
Laboratoř MS
Thu
Fri
Time-table for summer semester 2020/2021:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2020-12-03
For updated information see http://bilakniha.cvut.cz/en/predmet12541004.html