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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

VLSI System Design

The course is not on the list Without time-table
Code Completion Credits Range Language
AD0M34NSV Z,ZK 4 14KP+6KL Czech
Lecturer:
Tutor:
Supervisor:
Department of Microelectronics
Synopsis:

Introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems. Structure and design of digital and analogue integrated circuit subsystems. Integrated system description and synthesis using cell libraries and IP cores. Synchronization, power consumption and parasitics reduction issues. Testing and reliability of integrated systems. In seminars and labs, the hardware description language VHDL will be explained and used for practical design, synthesis and testing of a system on chip.

Requirements:

Successful presentation of semestral project and pass in the final test.

Syllabus of lectures:

1. VLSI system design, principles and hierarchy. Design methodology.

2. Levels of system description. Hardware description languages for behavioral and RTL description.

3. Code structure, semantics and syntax.

4. Assignments of hardware function, concurrent and sequential domains and their interpretation.

5. Hierarchy, design of parametric models and libraries. System description in SystemVerilog and SystemC.

6. Hardware platforms, target architectures, programmable and reconfigurable systems.

7. System on chip design, design re-use, Intellectual Property (IP) cores.

8. Behavioral synthesis: RTL model, algorithms and procedures. Logical synthesis: methods and constraints. Synthesis of topology. Control of system synthesis.

9. Models of integrated systems and structures, standards.

10. Testing and reliability. Fault models and methods of localization.

11. Verification flow and strategies.

12. Verification tools: simulators and models.

13. Test design and analysis: stimuli, responses and testbenches (design and architecture).

14. VLSI system project management, risk minimization, documentation, reviewing.

Syllabus of tutorials:

1. Design system ISE: introduction into integrated system design - entry, synthesis, implementation.

2. Design system ISE: functional, logical and timing analysis. Digital system model in HDL

3.HDL - description of combinational (buffers, decoders, multiplexers) and sequential (counters) functions.

4. HDL - hierarchical design and verification models (testbenches).

5. HDL - state automata description and design of complex sequential systems.

6. State automata description in the StateCad environment, end of model project.

7. Migration of model design into different architectures, design reuse.

8. IP core libraries, design using IP core generators.

9. Floor planning and timing analysis, design of architecture specific blocks.

10. Description of course works, used IP modules, test.

11. Practical design of integrated system based on FPGA or SoC.

12. Practical design of integrated system based on FPGA or SoC.

13. Practical design of integrated system based on FPGA or SoC.

14. Presentation of course works, correction test, account.

Study Objective:

The aim of the subject is introduction to basic building blocks, architecture and design methodologies of advanced VLSI systems.

Study materials:

1.P. J. Ashenden, The Designer's Guide to VHDL, Morgan Kaufmann, 2008

2. P. Chu, RTL Hardware Design Using VHDL: Coding for Efficiency, Portability, and Scalability, Wiley, 2006

3. P.K.Lala, Principles of Modern Digital Design, Wiley, 2006

Note:
Further information:
http://moodle.fel.cvut.cz/
No time-table has been prepared for this course
The course is a part of the following study plans:
Data valid to 2019-12-08
For updated information see http://bilakniha.cvut.cz/en/predmet1207106.html