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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2020/2021

Programmable IC Design

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Code Completion Credits Range Language
XP34PIC ZK 4 2P+2C Czech
Lecturer:
Pavel Hazdra (guarantor)
Tutor:
Pavel Hazdra (guarantor)
Supervisor:
Department of Microelectronics
Synopsis:

The aim of the course is to acquaint students with advanced methods of design, synthesis and verification of programmable systems and systems with high integration on the chip. Students will learn the basic building elements, architecture and

design procedures used to implement complex integrated systems, methods of describing them, and procedures

their synthesis. They will learn verification strategy, design and analysis of tests. This project-oriented course would

with the use of state-of-the-art EDA tools to implement a comprehensive programmable integrated system whose application would be linked to the topic of the dissertation.

Requirements:

c

Syllabus of lectures:

1. Integrated systems (IS), reasons and consequences of integration, technologies and methods of IS design and their production.

2. Application-specific integrated circuits, programmable integrated circuits and Systems on-Chip (SoC).

3. Complex programmable logic arrays (CPLDs), architectures, logic blocks and interconnection network.

4. Field Programmable Gate Arrays (FPGA) - principles, basic building blocks and architectures.

5. FPGA and SoC system design, principles and hierarchy. Design methodology.

6. Different levels of design description (system, RTL). Computer languages for hardware description (HDL).

7. System Verilog and VHSIC HDL languages ​for FPGA synthesis.

8. Behavioral synthesis: RTL model, algorithms and procedures.

9. Logical synthesis of FPGA blocks: procedures, algorithms and constraints.

10. Topology synthesis (floorplanning, mapping, deployment and interconnection). System architecture and data design.

11. Power supply and clock distribution in FPGA and SoC.

12. Design verification and testing.

13. Principles of design recycling, IP cores.

14. Strategy and economics of programmable integrated systems design.

Syllabus of tutorials:

Individual project solved with provided hardware (FPGA, SoC).

Study Objective:

The aim of the course is to acquaint students with advanced methods of design, synthesis and verification of programmable systems and systems with high integration on the chip.

Study materials:

Compulsory Literature:

[1] R. Sharma, Design of 3D Integrated Circuits and Systems, Chapman and Hall/CRC 2014

[2] Y. Li, Principles and Design in Verilog HDL, Wiley 2015

Recommended Literature:

[1] R. Woods, J. McAllister, G. Lightbody, Y. Yi, FPGA-based Implementation of Signal Processing Systems, Wiley

2017

[2] A. Sarkar et al., Low Power VLSI Design : Fundamentals, Walter de Gruyter GmbH 2016

[3] H. Jeong, Architectures for Computer Vision : From Algorithm to Chip with Verilog, John Wiley 2014

[4] B. Steinbach, Recent Progress in the Boolean Domain, Cambridge Scholars Publishing 2014

Note:
Further information:
https://moodle.fel.cvut.cz/course/view.php?id=3729
Time-table for winter semester 2020/2021:
06:00–08:0008:00–10:0010:00–12:0012:00–14:0014:00–16:0016:00–18:0018:00–20:0020:00–22:0022:00–24:00
Mon
Tue
Fri
roomT2:B2-s141j
Hazdra P.
11:00–12:30
(lecture parallel1)
Dejvice
Cvičebna K334
Thu
Fri
Time-table for summer semester 2020/2021:
Time-table is not available yet
The course is a part of the following study plans:
Data valid to 2020-09-25
For updated information see http://bilakniha.cvut.cz/en/predmet11433104.html