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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Architecture of Computer Systems

The course is not on the list Without time-table
Code Completion Credits Range Language
BI-APS Z,ZK 6 2P+2C Czech
Lecturer:
Tutor:
Supervisor:
Department of Computer Systems
Synopsis:

Students understand architectures of uniprocessor computers at the level of machine instructions, with emphasis to instruction pipelining and memory hierarchy. They know the main concepts of RISC and CISC architectures. They learn how modern computers work and how they are constructed. They learn about the techniques that today's processors use to increase the program execution speed. They have a basic knowledge allowing them to optimise their programs to fully exploit the processors. They get an idea about the trends in the area of computer architectures and how will they affect software. They also understand the architectures of vector processors, their use in todays microprocessors. They understand the principles of shared-memory multiprocessor system architectures and the issues of memory consistency.

Requirements:
Syllabus of lectures:

1. Computer performance evaluation, quantitative principles of computer architecture.

2. Instruction set architecture, RISC and CISC.

3. Introduction to pipelining, integer pipeline of RISC.

4. Advanced pipelining, hazard resolving, multicycle instructions.

5. Superscalar and superpipelined processors, pipelining of complex instructions.

6. Dynamic scheduling and dynamic branch prediction, limits of instruction-level parallelism.

7. [3] Memory hierarchy - cache, main memory, virtual memory.

8. Data-level parallelism, vector and SIMD architectures.

9. Shared memory multiprocessors, coherency and consistency.

10. Processor synchronization in shared memory multiprocessors.

11. Multiprocessor systems with distributed memory.

12. Perspectives of further development of computer systems.

Syllabus of tutorials:

1. Computer performance evaluation.

2. Measurement of computer performance with benchmark sets.

3. Instruction set of DLX, the role of compiler.

4. [2] Experiments with integer DLX pipeline.

5. [2] Simulation of pipelined DLX.

6. Evaluation of assignments, reserve.

7. Design and simulation of cache.

8. Performance simulation of cache.

9. [2] Simulation of DLXV.

10. Simulation of MESI protocol.

Study Objective:

Students learn how modern computers work and how they are constructed. They learn about the techniques that today's processors use to increase the program execution speed, and how they can optimize their programs to fully exploit the processors. They get an idea about the trends to expect in the area of computer hardware, and how will they affect software.

Study materials:

1. Hennesy, J. L., Patterson, D. A. Computer Organization and Design: The Hardware/Software Interface. Third Edition, Revised. Morgan Kaufmann, 2007. ISBN 0123706068.

Note:
Further information:
No time-table has been prepared for this course
The course is a part of the following study plans:
Data valid to 2019-09-19
For updated information see http://bilakniha.cvut.cz/en/predmet1124506.html