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CZECH TECHNICAL UNIVERSITY IN PRAGUE
STUDY PLANS
2019/2020

Seminars on Digital Design

The course is not on the list Without time-table
Code Completion Credits Range Language
XP36SCN ZK 4 2+2s Czech
Lecturer:
Tutor:
Supervisor:
Department of Computer Science
Synopsis:

This subject deals with the problems of realization and implementation of digital circuits - both combinational and sequential with respect to recent design platforms, programmable circuits and ASIC, timing, optimization and verification.

Requirements:

„PSC“ master courses knowledges.

Syllabus of lectures:

1.Combinational synthesis

Logic function representations (BDD, AIG, etc.), properties. Minimization, algebraic and Boolean methods, exact and heuristic methods. Technology mapping.

2.Sequential circuits

Automata theory, equivalence, decomposition, FSM implementation, technology mapping. Synchronous circuits optimization. Re-timing. Asynchronous sequential circuits

3.Combinatorial algorithms in logic synthesis

SAT solving, covering problem solving. Heuristic and exact methods. On-line optimization.

4.Electrical level and timing

Signals, noise immunity, reflections. electro magnetic compatibility, cross-talks, ground lines disturbances, clock distributions. Metastability, jitter. Analysis of synchronous circuits, clock domains relations, communication between clock domains. Technology properties with respect to timing. Timing models.

5.EDA systems

Structure, processes, design processes. Data import and export. Non-standard approaches.

6.Verification

Model checking, equivalence checking. Implicit and explicit models. PSC language. Assertions, libraries of assertions. Mixed verification methods.

Syllabus of tutorials:
Study Objective:

This subject will extend practical and theoretical skills obtained from „PSC“ master courses by recent and new trends in digital design field of research and practice.

Study materials:

G. D. Hachtel, F. Somenzi: „Logic Synthesis and Verification Algorithms“, Kluwer Academic Pub, 1996, 564 p.

S. Hassoun, T. Sasao, „Logic Synthesis and Verification“, Boston, MA, Kluwer Academic Publishers, 2002, 454 p.

Digital design world and Europe conferences, e.g. DDECS, DSD, ISWBP, ..

Note:
Further information:
No time-table has been prepared for this course
The course is a part of the following study plans:
Data valid to 2019-10-18
For updated information see http://bilakniha.cvut.cz/en/predmet1036206.html