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ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2019/2020

Digital Circuit Simulation

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah
MIE-SIM.16 Z,ZK 5 2P+1C
Přednášející:
Martin Kohlík (gar.), Jiří Douša
Cvičící:
Martin Kohlík (gar.)
Předmět zajišťuje:
katedra číslicového návrhu
Anotace:

Students gain information regarding the usage of basic tools for the design and simulation of VLSI (very large scale integration) digital circuits (VHDL, Verilog). They also get some knowledge about advanced tools System Verilog & SystemC.

Požadavky:

Design methods for combinational and sequential logic circuits, knowledge of number representations, knowledge of the circuit implementations of basic arithmetic operations.

Osnova přednášek:

1. Fundamental simulation principles, abstraction levels of digital circuit description.

2. [5] VHDL: Entities, architectures, overview of data types and corresponding operations, delta delay, inertial delay, transport delay, sequential environment, signal attributes, resolution function, synthesizable constructs of the language, creating user libraries, data-flow description, blocks, guarded blocks, guarded assignment statements, guarded signals, structural description, configuration of structural architectures, creating tests.

3. [4] Verilog: Analogy with VHDL, modules and their interfaces, overview of data types and operations, sequential environment, nondeterministic Verilog behavior, blocking and nonblocking assignments, parallel environment, nets and strengths, synthesizable constructs of the language, modeling structures, primitive elements, creating tests.

4. [2] Modern trends in the area of digital circuit simulation (transaction level modeling, coverage driven testbench, assertions). SystemC & SystemVerilog: overall characteristic of the system. Methods of parallel simulation.

Osnova cvičení:

1. Getting acquainted with the MODELSIM system. Presentation of examples in the VHDL language.

2. Working on the first project.

3. Working on the first project.

4. Working on the second project.

5. Working on the third project.

6. Final evaluation and assessment.

Cíle studia:

The goal of the course is to acquaint students with the principles of quasi-parallel simulation of structures, as well as with the properties of the above-mentioned languages and their use for simulation and synthesis.

Studijní materiály:

Dewey, A. M. Analysis and Design of Digital Systems with VHDL. International Thomson Publishing, 1996. ISBN 0534954103.

Cohen, B. VHDL Coding Styles and Methodologies. Springer, 1999. ISBN 0792384741.

Ciletti, M. D. Advanced Digital Design with the Verilog HDL. Prentice Hall, 2002. ISBN 0130891614.

Bhasker, J. A SystemC Primer. Star Galaxy Publishing, 2004. ISBN 0965039129.

Grötker, T., Liao, S., Martin, G., Swan, S. System Design with SystemC. Springer, 2002. ISBN 1402070721.

Poznámka:

Informace o předmětu a výukové materiály naleznete na https://courses.fit.cvut.cz/MIE-SIM/

Další informace:
https://courses.fit.cvut.cz/MIE-SIM/
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 18. 10. 2019
Aktualizace výše uvedených informací naleznete na adrese http://bilakniha.cvut.cz/cs/predmet4903206.html