ČESKÉ VYSOKÉ UČENÍ TECHNICKÉ V PRAZE
STUDIJNÍ PLÁNY
2018/2019

# Testing and Reliability

Předmět není vypsán Nerozvrhuje se
Kód Zakončení Kredity Rozsah Jazyk výuky
MIE-TSP.16 Z,ZK 5 2P+2C
Přednášející:
Petr Fišer (gar.)
Cvičící:
Petr Fišer (gar.), Martin Daňhel
Předmět zajišťuje:
katedra číslicového návrhu
Anotace:

Students gain knowledge about circuit testing and about methods for increasing reliability and security. They will get practical skills to be able to prepare a test set with the help of the intuitive path sensitization and to use an ATPG for automatic test generation. They will be able to design easy testable circuits and systems with built-in-self-test equipment. They will be able to analyze and control reliability and availability of the designed circuits.

Digital IC design and VHDL.

Osnova přednášek:

1. Introduction, terminology, defects, faults

2. Test generation for combinational circuits

3. Automatic Test Patterns Generation algorithms (ATPG)

4. Sequential circuits testing, fault simulation

5. Dependability, increasing dependability

6. Dependability models, dependability computation

7. Design for testability

8. Sequential circuit testing - scan design

9. Interconnect testing, SoC and NoC testing

10. Built-in self-test (BIST)

11. Test compression

12. Memory and FPGA testing

Osnova cvičení:

1. Introduction to the course

2. Faults in digital circuits

3. D-Algorithm, Boolean Differential Calculus

4. Tests generation for combinational circuits

5: Testing of sequential circuits

6. ATPG Atalanta

7. Reliability Block Diagrams

8. Markov reliability models

9. Fault Tree Analysis and other reliability models

10. Reliability standards

11. Assessment test, Design of the BIST

12. Assessment

Cíle studia:

Students will gain an overview about circuit testing and about methods for increasing reliability and dependability. Students will understand the complexity of fault detection, fault localisation, reliability evaluation and enhancement by solving practical examples and projects. They will be able to optimize the trade-off between introduced redundancy and the measure of testability and dependability of the proposed system. Students will obtain a competence for getting a position of testing engineer in the teams working on complex digital designs.

Studijní materiály:

O. Novák, E. Gramatová, and R. Ubar, „Handbook of testing electronic systems“. Praha: Publishing House of CTU, 2005. ISBN 80-01-03318-X.

R. Velazco, D. McMorrow, J. Estela, „Radiation Effects on Integrated Circuits and Systems for Space Applications“, Springer, 2019, ISBN: 978-3-030-04660-6, 401 p.

Z. Navabi, „Digital System Test and Testable Design“, Springer, 2011, ISBN 978-1-4419-7547-8, p. 435

L. D., Protheroe D., „Digital circuit testing and design for testability“, in Design of Logic Systems, Springer, Boston, MA, ISBN: 978-0-412-42890-6, 1992

F. C. Wang, „Digital Circuit Testing: A Guide to DFT and Other Techniques“, Elsevier, ISBN 978-0-12-734580-2, 1991, 228 p.

F. da Silva, T. McLaurin, and T Waayers, „The Core Test Wrapper Handbook: Rationale and Application of IEEE Std. 1500“, Frontiers in Electronic Testing, 2006-th Edition, Springer, ISBN 978-0387307510, 2006, 276 p.

Poznámka:

Rozsah: 2p+2c

Další informace:
https://moodle.fit.cvut.cz/course/view.php?id=207
Pro tento předmět se rozvrh nepřipravuje
Předmět je součástí následujících studijních plánů:
Platnost dat k 19. 7. 2019
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